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Life at Cadence

Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
• 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

Introduction to the Linux Kernel Message System

One of the most common problem reports related to Virtual Platforms running Linux…

• 6 min read
Virtual System Platform , virtual platforms , GDB , VAP , cadence , ring buffer , uncompressing Linux , virtual prototypes , booting Linux , embedded software , VSP , Imperas , software development , Zynq virtual platform , linux , Zynq-7000 , Embedded Linux , ESL , System Design and Verification , kernel messaging system , Andrews

System, PCB, & Package Design 

What's Good About PCB SI Adaptive Mesh Generation? 16.5 Has Many New Enhancements

The 16.5 PCB SI product’s rectangular mesh scheme is used for shapes, cutouts, slots…

• 2 min read
PCB SI , PCB , SI , PI , PCB PI , PDN , Signal Intregrity , SI bus analysis , SigXP UI , PCB Signal and power integrity , "PCB SI" , High Speed , Allegro 16.5 , SPB , High-Density Interconnect , full wave , Signal Integrity , full-wave , PDN Analysis , OrCAD PCB SI , field solver , Allegro PCB SI , PCB design , "PCB PI" , adaptive mesh generation , Grzenia , SPB16.5 , SI analysis and modeling , Meshing , HDI , Allegro

Analog/Custom Design

Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM

Even though it's been over 2 months since this year's Design Automation Conference…

• 3 min read
real number modeling , DAC , uvm , IP , A/MS , Verilog-AMS , analog , co-simulation , Mixed-Signal , analog behavioral models , analog/mixed-signal , model validation , RNM , metric-driven verification , VHDL-AMS , assertions , mixed signal , mixed-signal design , wreal , real number models , Design Automation Conference , SPICE , mixed-signal verification , verification , stmicroelectronics , real number

System, PCB, & Package Design 

Customer Support Recommended – Appnote on Implementing the Force-Sense Kelvin Co…

The use of separate force (F) and sense (S) connections (often referred to as a Kelvin…

• 2 min read
PCB , Kelvin connection , Allegro Design Entry , customer support , part developer , DEHDL , PDV Symbol , Allegro 16.5 , Appnotes , PCB Editor , Design Entry HDL , Appnote , symbol , Force-Sense , PCB design , 16.5 , force sense , SPB16.5 , ConceptHDL , application note , Schematic , Allegro , Kelvin

System, PCB, & Package Design 

What's Good About APD’s Wire Bond Settings Groups? You’ll Need the 16.5 Release to…

The 16.5 Allegro Package Design (APD) product has been modified to provide a different…

• 4 min read
PCB , PCB Layout and routing , packaging , APD , Allegro 16.5 , Wirebond , Allegro Package Designer , wire bond settings groups , PCB design , Grzenia , wire bond , Allegro

Verification

Report From Silicon Valley With Application Engineer Bin Ju

Luckily I was able to track down my very busy colleague Bin Ju between assignments…

• less than a min read
Joe Hupcey III , ABV , Formal Analysis , Bin Ju , formal , video , formal apps

Verification

Improving SimVision Fonts for Ubuntu

This article is a follow-up on an early 2012 article about using Incisive and Virtual…

• 4 min read
Virtual System Platform , virtual platforms , System Design and Verification , VSP , Incisive , Ubuntu , Ubuntu 12.04 , SystemC

Verification

A “Reflection” on Chip-Level Debugging with Specman/e and SimVision

Last week, a favorite customer of mine called me in a panic, just days from tape…

• 6 min read
Specman , Specman/e , debug , simvision , Incisive , SimCompare , e language , chip-level debugging , Funcional Verification , reflection , irun , testbench , simulation

System, PCB, & Package Design 

What's Good About Allegro PCB Router Routing Changes? 16.5 Has a Few New Enhancements

The 16.5 Allegro PCB Router has a couple new improvements I’ll cover today – Embedded…

• 2 min read
PCB , PCB Layout and routing , embedded components , Routing , route quality , Allegro 16.5 , diff pair , PCB Editor , differential pair , Allegro router , PCB design , Grzenia , Allegro

System, PCB, & Package Design 

What's Good About Allegro PCB Editor GUI updates? See for Yourself in 16.5!

The 16.5 Allegro PCB Editor release contains several updates to the Graphical User…

• 2 min read
PCB , PCB Layout and routing , Allegro GUI , status bar , super filter , Allegro 16.5 , PCB Editor , PCB design , 16.5 , Allegro PCB Editor , etch class , Allegro

SoC and IP

Cadence Video Demonstrates PCIe Gen3 IP Silicon Performance

It is not often that an IP provider gets to showcase their IP performance in a real…

• 1 min read
controller IP , Design IP , IP , PCI Express 3.0 , Gen3 , video , Matta , storage , SAS RAID , PCIe , PCIe Gen3 , PCI Express Gen3 , PCI Express

Verification

SimVision Watch Window Now Accommodates Specman Watch Items

Starting from version 12.1, the SimVision Watch Window accommodates Specman watch…

• less than a min read
AF , Specman , gui , watch window , debug , Functional Verification , specview , Specman watch , simvision , SimVision watch window , watches , Chudnovsky

Digital Design

In Case You Missed It – The Most Popular EDI System Knowledge Content Published in…

I mentioned in my first blog one of my roles in customer support is to identify and…

• 2 min read
EDI , AOCV , advanced on-chip variation , Cadence Online Support , encounter , OCV , Digital Implementation , Encounter Digital Implemention , app notes

Digital Design

How To: Bring Up Encounter "man" Pages from a UNIX Prompt

Okay, this one is too cool not to share. The other day a customer and I were trying…

• 1 min read
documentation , Unix prompt , EDI , man pages , encounter digital implementation system , Tips , help , Digital Implementation , man , tricks

Verification

Video: Interview with Professional Teenage Technology Coach Kristine Bonhoff

Over the past several years at various EDA trade events, one of the more popular…

• 1 min read
Joe Hupcey III , Kristine Bonhoff , interview , video , EDA360 , apps , teen tech

Verification

Product Update: New Assertion-Based Verification IP (ABVIP) Available Now

Verifiers rejoice: R&D has just released all-new Assertion-Based Verification IP…

• 2 min read
Incisive Formal Verifier , Jose Barandiaran , ABV , Functional Verification , ABVIP , formal , formal apps , assertions , IEV , Incisive Enterprise Simulator (IES) , Formal verification , IFV , verification , Assertion-based verification , IES-XL

Digital Design

10 Encounter Tips and Tricks You May Not Be Aware Of

In looking over the shoulders of Encounter users over the years I've found there…

• 1 min read
EDI , Routing , power routing , encounter digital implementation system , IC layout , NanoRoute , Tips , encounter , tips and tricks , Digital Implementation , signal routes , log file , tricks , tcl

Verification

Video: DVCon 2012 Digital-Mixed Signal (DMS) Expert Neyaz Khan on UVM Mixed Signal…

E-mail reminders for the DVCon 2013 Call For Abstracts prompted me to look through…

• 1 min read
digital mixed-signal , AMS , uvm , Joe Hupcey III , verification strategy , Verification methodology , Functional Verification , UVM-MS , Neyaz Khan , Mixed Signal Verification , Mixed-Signal , DVcon , Maxim Semiconductor , verification

Verification

My Constraint was Ignored – Is it a Tool Bug? – Part 2

In a previous post we showed some cases of user code that can cause ignored constraints…

• 3 min read
AF , IntelliGen , Specman , debug , Functional Verification , Generation , e language
CDNS - Fix Layout Hompage