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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
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Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Quickplace Overlap? Check Out 16.6!

Just a very "quick read" on a new option for Quickplace this week. The Allegro PCB…

• less than a min read
PCB , PCB Layout and routing , Allegro GUI , Allegro 16.6 , Overlap components by , Placement Edit , place replicate , SPB , PCB Editor , Layout , Quickplace , PCB design , Grzenia , Allegro PCB Editor , Allegro

Verification

The Internet of Things – the Next Growth Driver, Enabled by High-Level Synthesis…

The electronics industry has enjoyed constant growth while undergoing constant transformation…

• 3 min read
High-Level Synthesis , DAC , ASIC , microcontrollers , microprocessors , TLM , processors , TLM 2.0 , C , the internet of things , programmable world , Internet , SystemC , C-to-Silicon Compiler , HLS , microcontroller , C++

Analog/Custom Design

Virtuosity: 10 Things I Learned in April by Browsing Cadence Online Support

I'll confess: I didn't learn all of this strictly by browsing https://support.cadence…

• 2 min read
AMS , custom/analog , layout-dependent effects , Rapid Adoption Kit , 20nm , Virtuoso , Virtuosity , mixed signal , Custom IC Design

System, PCB, & Package Design 

What's Good About AMS Data Precision Options? They’re in the 16.6 Release!

Just a brief blog today to introduce that 16.6 Allegro AMS Simulator (PSpice) now…

• less than a min read
Cadence Design Systems , AMS , cadence , AMS simulator , OrCAD Capture , Allegro AMS , PSPICE , design , OrCAD , AMS simulation , Grzenia

Analog/Custom Design

Things You Didn't Know About Virtuoso: Delta Markers in ViVA

This article is dedicated to the gentleman I sat next to at lunch at CDNLive a while…

• 3 min read
Analog Design Environment , ViVa-XL , Virtuoso IC6.1.5 , IC615 , IC 6.1.5 , delta markers , Analog Design Environment , ViVA , Custom IC Design

Verification

Mode Support for SimVision “Stop Simulation” Button

Prior to Incisive Enterprise Simulator (IES) 12.1, clicking the SimVision "Stop Simulation…

• 1 min read
AF , Specman , debug , Functional Verification , stop simulation , simvision , Incisive , e language , stop Specman , IES

System, PCB, & Package Design 

What's Good About Capture’s Save Command? 16.6 Has a Few New Enhancements!

Just a quick blog this week to mention a couple productivity enahancements for Capture…

• 1 min read
capture , Cadence Design Systems , Allegro Design Entry , Allegro 16.6 , Design Entry CIS , Capture CIS , Capture-CIS , SPB , Front-end PCB design , design , Design Entry , Grzenia , Allegro

System, PCB, & Package Design 

Turn GDSII Data into Intelligent Die Components with 16.6 Cadence APD/SiP Tools

As we all know, there are many file formats in which an IC package designer will…

• 3 min read
Cadence Design Systems , SiP , IC Package , IC Packaging , GDSII , packaging , Digital SiP design , Advanced Package Router , stream , 16.6 , GDS-II , APD , IC Packaging & SiP design , Allegro Package Designer , IC packaging documentation , SiP Layout

System, PCB, & Package Design 

Customer Support Recommended - Instance and Occurrence Modes of Design Annotation…

Assigning reference designators for the schematic instances is a very vital part…

• 5 min read
PCB , 16.01 , capture , "capture CIS" , hierarchy , cadence , OrCAD Capture , 16.6 , Capture CIS , Capture-CIS , hierarchical schematics , Appnotes , Appnote , "PCB design" , OrCAD , PCB design , 16.5 , application note , PCB Capture , Schematic

Verification

Creating Virtual Platform Models

One of the most common questions asked about virtual platforms is:Who creates the…

• 4 min read
VSP Log Viewer , virtual prototoypes , virtual platforms , TLM , virtual platform models , cadence , TLM-2 , System Design and Verification , TLM 2.0 , SystemC modeling , TLM-2.0 , timgen , SystemC , Model creation , Cadence Virtual System Platform

System, PCB, & Package Design 

What's Good About ADW’s Design Migration? 16.6 has many new enhancements!

Prior to the Allegro Design Workbench (ADW) 16.6 release, the migration process required…

• less than a min read
Allegro 16.6 , cadence , 16.6 , Allegro Design Workbench , design data management , design , Grzenia , library , ADW , Allegro

Analog/Custom Design

SKILL for the Skilled: Part 8, Many Ways to Sum a List (Closures -- Functions with…

In the past several postings to this blog, we've looked at various ways to sum a…

• 8 min read
Team SKILL , lexical closures , programming , Jim Newton , closures , sum a list , IC615 , SKILL for the Skilled , summing , Lisp , SKILL++ , SKILL

Verification

Develop For Debugability – Part II

Looking at Coding Styles for Debug In this blog post we are going to discuss 3 different…

• 3 min read
AF , Specman , Specman/e , debug , Functional Verification , debugability , debuggability , e language , Incisive Enterprise Simulator (IES) , Daniel Bayer

System, PCB, & Package Design 

What's Good About FSP’s Design Compare? Check Out 16.6!

The 16.6 Allegro FPGA System Planne r (FSP) product has an extremely helpful Design…

• 2 min read
PCB , PCB Layout and routing , Allegro 16.6 , FPGA-PCB Co-Design , FPGA System Planner , 16.6 , Taray , FPGAs , SPB , PCB Editor , Design Entry HDL , Layout , design , FSP , PCB design , Grzenia , comparing constraints , FPGA , Allegro , FPGA: PCB

Digital Design

Answers to Top 10 Questions on Performing ECOs in EDI System

Applying ECOs to a design can be complex, stressful and error prone so it's important…

• 6 min read
ECO , Cadence EDI System , LEC , encounter digital implementation system , tips and tricks , Synthesis , mmmc

System, PCB, & Package Design 

What's Good About DEHDL’s Constraints Comparison? The Secret's in the 16.6 Release

The Allegro 16.6 Design Entry HDL release provides designers a mechanism to compare…

• 2 min read
PCB , Allegro Design Entry , Constraint-driven PCB Design flow , constraint databases , Allegro 16.6 , 16.6 , property , PCB Editor , Constraint Manager , Layout , design , constraint difference , PCB design , Grzenia , Schematic , Allegro

Analog/Custom Design

Virtuosity: 10 Things I Learned in March by Browsing Cadence Online Support

Topics in March include advanced analysis in ADE GXL, taking advantage of lots of…

• 2 min read
Analog Design Environment , Virtuoso IC6.1.5 , Virtuoso Space-based Router , Rapid Adoption Kit , IC615 , IC 6.1.5 , ADE , VLS GXL , Virtuoso Analog Design Environment , Monte Carlo , Virtuoso Layout Suite L , Virtuoso , ADE-GXL , Analog Design Environment , ADE-XL , VLS L , AMS simulation , Custom IC Design , modgens , RAKs , Virtuoso Layout Suite , Virtuoso Layout Suite GXL , VLS XL , SKILL , Virtuoso Layout Suite XL

System, PCB, & Package Design 

Corral Your Selections with New Lasso and Path Modes in 16.6 APD and SiP

The level of ease and efficiency you experience in selecting the items needed for…

• 2 min read
package , SiP , IC Package , IC Packaging , packaging , Digital SiP design , 16.6 , APD , wirebonds , IC Packaging & SiP design , Allegro Package Designer , IC packaging documentation , APD 16.6 , SiP Layout , wirebonding , IC Package Physical layout and co-design

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Generic Cross-Section Files? See for Yourself…

Beginning with the Allegro PCB Edito r 16.6 release, you are provided a methodology…

• 2 min read
PCB , PCB Layout and routing , ECSets , Constraint-driven PCB Design flow , constraint databases , Allegro GUI , Allegro 16.6 , electrical constraints , 16.6 , SPB , PCB Editor , Constraint Manager , Layout , design , "PCB design" , constraint difference , PCB design , Constraints , Grzenia , Allegro PCB Editor
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