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What's Good About AMS Multi-Core Engine Support? It’s in the 16.6 Release!

The 16.6 AMS Simulator (PSpice) release now includes support for multi-core capabilities…

Jerry GenPart 8 Jan 2014 • 2 min read

Cadence Design Systems , AMS , Allegro 16.6 , cadence , Allegroro AMS Simulator (PSpice) , AMS simulator , 16.6 , PSPICE , AMS simulation , Grzenia

System, PCB, & Package Design

Customer Support Recommended - Implementing Jumpers in Allegro PCB Editor

Over the time, jumpers have found their importance in multiple applications . The…

Naveen 7 Jan 2014 • 3 min read

PCB Layout and routing , PCB Editor , vias , PCB design , jumpers

Verification

New Capabilities in the C-to-Silicon Compiler 2013 Releases

2013 was a banner year for high-level synthesis and C-to-Silicon Compiler in particular…

Jack Erickson 6 Jan 2014 • 4 min read

13.1 , C-to-Silcon , 13.2 , pipeline functions , high level synthesis , RTL schematic

RF Engineering

Have You Tried the New Transmission Line Library (rfTlineLib)?

Happy New Year! Have you tried the new Transmission Line Library (rfTlineLib)…

Tawna 3 Jan 2014 • 4 min read

RF , RF Simulation , transmission line , RFIC , Wilsey , Spectre RF , rfTlineLib , spectreRF , SpectreRF tutorials

Analog/Custom Design

Virtuosity: 12 Things I Learned in November by Browsing Cadence Online Support

New content on a wide variety of topics in November. Product Information 1. Cadence…

stacyw 18 Dec 2013 • 2 min read

EAD , AMS Designer , Virtuoso , AMS simulation , PVS

RF Engineering

SpectreRF Tutorials and Appnotes... Shhhh... We Have a NEW Best Kept Secret!

It's been a while since you've heard from me...it has been a busy year for sure.…

Tawna 17 Dec 2013 • 1 min read

RF Simulation , wireless , Wilsey , tutorial , spectreRF , Appnote , RF design , transmission lines , harmonic balance , SpectreRF tutorials

Verification

Practical Guide to the UVM for $15 - Virginia, There is a Santa!

Wondering what to get the verification engineer on your list? You know, the one with…

Adam Sherer 13 Dec 2013 • less than a min read

funtional verification , SystemVerilog , scoreboard , uvm , IEEE 1800 , Verification methodology , UVMWorld , OVM , Incisive Enterprise Simulator , Register Package , SoC , IEEE1800 , Register Layer , IES , IUS , VMM

Analog/Custom Design

Support for Low Power Mixed Signal Designs in Virtuoso Schematic-XL

Why is There a Need for Low Power Solutions? With an increase in the demand for…

DeveshJain 10 Dec 2013 • 8 min read

Low Power , mixed signal design , mixed-signal methodology , mixed signal solution , CPF , LVS , cdl , Schematics-XL , Mixed-Signal , analog/mixed-signal , Virtuoso , mixed signal

System, PCB, & Package Design

Take Your Via Structures from Ordinary to Exceptional with 16.6 IC Packaging Advanced…

Via structures—those reusable patterns of conductor clines and vias designers rely…

Jeff Gallagher 5 Dec 2013 • 5 min read

IC Packaging and SiP Design , SiP , IC Packaging , packaging , Analog and RF SiP design , 16.6 , IC package design , APD , wirebonds , APR , IC Packaging & SiP design , BGA , Allegro Package Designer , IC packaging documentation , early adopter , APD 16.6 , SiP Layout , wirebonding , IC Package Physical layout and co-design

SoC and IP

Great Progress with Ethernet Standards Development

The IEEE 802 local area networking standards committee held its plenary meeting in…

ArthurM 2 Dec 2013 • 2 min read

controller IP , Verification IP , PoDL , 802.3bp , Design IP , IP , cadence , 802.3bs , PHY , 400Gpbs , 40Gbps , Automotive Ethernet , 802.3bt , 802.3bq , 802.3br , 100Gbps , 802.3bu , IEEE 802.3 , Ethernet , 802.3bm , Marris , 802.3bj , semiconductor IP , Ethernet PHYs , Power over Data Lines , Power over Ethernet

Verification

Covering Edges (Part I) – Cool Automation

With random generation, most of the fields are due to be quite well covered. If…

teamspecman 2 Dec 2013 • 2 min read

AF , e language , Funcional Verification , functional coverage , coverage driven verification (CDV) , Aspect Oriented Programming

Analog/Custom Design

SKILL for the Skilled: SKILL++ hi App Forms

One way to learn how to use the SKILL++ Object System is by extending an application…

Team SKILL 1 Dec 2013 • 10 min read

layout hierarchy , Jim Newton , schematic hierarchy , object orientation , Layout , Virtuoso , object system , software development , design hierarchy , SKILL++ , SKILL , Schematic

Verification

Accelerating Code Coverage Using Palladium XP Rapid Adoption Kit

Code coverage is an effective tool in the verification process, giving insights into…

SumeetAggarwal 25 Nov 2013 • 1 min read

IMC , System level verification and validation with Palladium XP , Rapid Adoption Kits , Palladium XP , UniCov Databases , Accelerated Code Coverage , RAKs , Accelerated Coverage , Assertions and Functional Coverage with covergroups.

System, PCB, & Package Design

Optimize Your PCB Decoupling Capacitors and Remain a Person of Integrity

How much integrity is too much? If your PCB designs apply one or more decoupling…

TeamAllegro 22 Nov 2013 • 2 min read

PDN , Power Integrity , High Speed , OptimizePI , Power Delivery Network , power-aware SI , decap , Allegro Sigrity

Analog/Custom Design

SKILL for the Skilled: Simple Testing Macros

In this post I want to look at an easy way to write simple self-testing code. This…

Team SKILL 21 Nov 2013 • 5 min read

Team SKILL , programming , shuffle , Jim Newton , SKILL for the Skilled , macros , Lisp , SKILL++ , SKILL

Verification

High-Level Synthesis Now Spans the Datapath-Control Spectrum

When we talk to prospective high-level synthesis (HLS) customers, one of the slides…

Jack Erickson 20 Nov 2013 • 1 min read

antenna interface controller , controll logic , ITRI , NAND flash controller , C-to-Silcon , Freescale , System C , rtl compiler , data access controller , datapath , high level synthesis , Fujitsu Semiconductor

System, PCB, & Package Design

Signal Integrity Analysis of Serial Data Channels—A Complete Solution Using Allegro…

Back in the day, when challenged to transfer data faster, we increased the width…

TeamAllegro 18 Nov 2013 • 1 min read

Serial link analysis , High Speed , IBIS-AMI , Signal Integrity , SI analysis and modeling , SystemSI , Allegro Sigrity

Analog/Custom Design

Virtuosity: 12 Things I Learned in October by Browsing Cadence Online Support

Lots of routing, a little AMS, and finishing off with some fun... Application Notes…

stacyw 15 Nov 2013 • 3 min read

SystemVerilog , AMS , PAD , Virtuoso Space-based Router , VSR , Routing , Spectre , mixed signal

Digital Design

11 Things I Learned by Browsing Cadence Online Support

I guess by now most of us are already familiar with Rapid Adoption Kits (RAKs). These…

MJ Cad 14 Nov 2013 • 3 min read

Digital Implementation forums , How To , Cadence EDI System , power routing , Floorplanning , encounter digital implementation system , beginner , NanoRoute , training , Appnotes , Top Ten , digital implementation , Cadence Encounter Power System , GigaOpt , Digital Implementation , Encounter Digital Implementation , crosstalk , app notes , high performance , Rapid Adoption Kits , encounter power system , OpenAccess , Floorplanning and Prototyping , RAKs , FlipChip

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