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The Power of Shifting Left: Cadence Accelerating Innovation with Arm

In semiconductor design, projects are remembered for their extremes—legendary successes…

Arif Khan
• 3 min read
ucie , xcellium , IP , featured , PHY

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die
SoC and IP
Latest blogs

MIPI DevCon 2016 – Mobile and Beyond

MIPI DevCon 2016 – Mobile and Beyond The word “beyond” may bring up thoughts of…

• 6 min read
MIPI Alliance , ADAS

Less is More With MIPI I3C

There is little doubt that Internet of Things has become the next big thing in business…

• 1 min read
peripherals , IoT , MIPI , i2c , sensors , hdr , I3C , sensewire , hub

Building the Cars of the Future

The big buzz in the automotive industry lately is autonomous driving vehicles. Companies…

• 3 min read
Verification IP , VIP , Automotive Ethernet , CAN , automotive electronics , Ethernet , Design IP and Verification IP , Lin

Fastest Octal SPI Flash Interface Available Now From Cadence

Flash memory is being utilized in computers and electronic devices found in Automotive…

• 1 min read
PHY , octal spi , spi , nor flash

Cadence at Flash Memory Summit 2016: Octal SPI, eMMC 5.1, ONFi 4, and Tensilica SSD…

If you design with flash memory components or IP solutions, head on over to the Santa…

• 1 min read
Verification IP , Design IP , Memory , VIP , Tensilica , semiconductor IP , Design and Verification IP , Design IP and Verification IP , memories

Needs of Energy-Efficient Networking While Using 10 Gigabit Ethernet

Growing deployment level of 10 Gigabit Ethernet in datacenters and automotive infotainment…

• 1 min read
10G-KR , Ethernet

PCI Express Trends and News at PCI-SIG 2016

PCI-SIG Developers Conference 2016 is now history, taking place at the Santa Clara…

• 1 min read
PCIe Gen4 , 10G-KR , SerDes , PCI Express

How to Create a Working IoT Sensor in One Month

Cadence and ARM have created an IoT IP reference sub-system that can speed system…

• less than a min read
sensor , IoT , ARM , IoT subsystem , IoT sensor

Can You See Me? Putting Neural Networks in Everyday Devices

Neural networks have become very popular today due to their use in leading-edge technology…

• 1 min read
CVPR , Chris Rowen , Computer Vision , Tensilica , neural networks , CNN , image processing

The PCIe 4.0 Era Continues at PCI-SIG Developers Conference 2016

PCI-SIG is a leading event in cloud infrastructure transformation, which is markets…

• 1 min read
PCIe Gen4 , 10G-KR , SerDes , PCI Express

Compatibility Is Good, But Compliance Is Better—Certifying for VESA DisplayPort

For all IP providers, the ultimate proof of quality of their product is certification…

• 1 min read
IP , Jacek Duda , DisplayPort , MHL , USB , compliance , VESA , HDMI , Alternate Mode , certification

DAC 2016—Drink from the Expert Bar and Then at the Denali Party

Black-belt interface and memory protocol technologists will be at your disposal at…

• 2 min read
DAC , IP , Denali Party , Denali

16Gbps Multi-link, Multi-protocol SerDes at the 21st IEEE European Test Symposiu…

The 21 st European Test Symposium (IEEE EST) took place in Amsterdam (Netherlands…

• 1 min read
16gbps , PCIe Gen4 , SerDes , Multi-link , multi-protocol

What Memory Best Fits Your Application?

With highly effective DDR4 and LPDDR4 class memories, it’s not always easy to know…

• 1 min read
DDR4 , LPDDR4 , 4266 , 3200

Continued Strength of the Design&Reuse IP-SoC India

Design&Reuse events are always exciting for their draw of an IP-centric audience…

• 1 min read
PCIe Gen4 , 10G-KR , SerDes

Cadence and Hardent demonstrate high resolution display interface for Automotive

At Cadence we aim to enable our customers’ need to reduce their own design time and…

• 1 min read
Hardent , Design IP , MIPI Alliance , CDNLive , DIP , MIPI , DSI , DSC

High Speed East-West Interconnect at the Open Server Summit

This year’s Open Server Summit served up plates full of data…if it wasn’t obvious…

• 1 min read
PCIe Gen4 , 10G-KR , SerDes

CDNLive Silicon Valley 2016—The Bigger IP Picture

When a presentation makes us think about an industry on a whole new level and rethink…

• 1 min read
CDNLive , ip cores , Design IP and Verification IP

50 Years of Turning Optical Dreams into Reality

Anaheim Convention Center (CA) was the center of a spectacle of technology that continues…

• 3 min read
Optical , PCIe Gen4 , OFC , Fiber , PCIe

Design IP Customer and Technology Presentations at CDNLive Silicon Valley, April…

We have an exciting Design IP track at CDNLive Silicon Valley again this year. ARM…

• 1 min read
Design IP , CDNLive , PCIe Gen4 , DIP , SerDes , Silicon Valley

Tech Shanghai Drives Innovation by Overcoming Challenges

Far more often than we imagine, we think about China within the context of the complicated…

• 2 min read
China , DDR4 , PCIe Gen4 , tech shanghai

TSMC’s Technology Symposium 2016 is the Place to be for Innovation

At this year’s Technology Symposium, TSMC disclosed that they will provide two N7…

• less than a min read
DDR4 , LPDDR4 , TSMC Tech Symposium , ip cores , PCIe , 16FF+

DDR/LPDDR 4/3 Combo PHY in TSMC 28HPC Silicon Proven at 2400 Mbps

Back in October we announced the TSMC 28HPC tapeout of our DDR/LPDDR 4/3 Combo PHY…

• 1 min read

The most powerful feature of USB Type-C – Power Delivery

One thing that all mobile electronics devices have in common is that they all need…

• 1 min read
USB 3.0 , Jacek Duda , Consumer Electronics Show , CES , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

See Demonstration Video of PCIe 4.0 PHY IP in TSMC 16FF+

Did you miss DesignCon this year? If so, you also missed the demonstration of our…

• less than a min read
DesignCon , PCIe Gen4 , pcie4 , SerDes

DesignCon Demonstration of IP for PCIe 4.0 and 16Gbps Multi-Protocol PHY

We enjoyed sharing our latest news with the many people who visited our booth at…

• less than a min read
DesignCon , PCIe Gen4 , pcie4 , Design IP and Verification IP , SerDes

New 16Gbps Multi-link, Multi-protocol SerDes PHY Enhances Datacenter Connectivit…

PCIe Gen4 is bringing new possibilities to servers and virtualization. The interface…

• 1 min read
PCIe Gen4 , pcie4 , 16Gbps PHY IP , SerDes , SerDes IP

The Future of High-Speed SerDes

David Axelrad, product marketing manager, SerDes IP, presents Cadence's position…

• less than a min read
PCIe Gen4 , pcie4 , SerDes , gsa
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