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Breakfast Bytes: Legato: Making the Bathtub Wider and Deeper

Paul McLellan

Yesterday's post Automotive Reliability: The Bathtub Curve introduced automotive reliability and how transistors suffer from early life failure, hopefully nothing in mid-life, and then aging and wearout. This is summarized in the diagram be...
- 22 Apr 2020
System, PCB, & Package Design : BoardSurfers: Training Insights - Fundamentals of PDN for Design and PCB Layout

mrigashira

What is a Power Distribution Network (PDN) after all but resistance, inductance, and capacitance in the PCB and components? And, of course, it is there to deliver the right current and voltage to each component on your PCB. But is that all? Are there oth...
- 21 Apr 2020
System, PCB, & Package Design : IC Packagers: You Can Leave Your (Molding) Cap On…

Tyler

Molding caps aren’t something we talk about too frequently around here. We all know they exist, and they serve an important purpose of protecting the delicate die from potentially harsh environmental conditions. They impact how well heat can be...
- 21 Apr 2020
Breakfast Bytes: Automotive Reliability: The Bathtub Curve

Paul McLellan

There are a lot of aspects of automotive reliability. The same goes for aerospace and medical, which have additional issues, too, so I'm going to focus on automotive. I'm also going to focus on semiconductor reliability, although obviously other com...
- 21 Apr 2020
Breakfast Bytes: Fourth 4G Network Goes Live in Japan

Paul McLellan

So your first thought on reading the title to this post might be that having to stay at home has finally got to me and made my brain turn to mush. Or perhaps that I'm really, really short of material to write about. After all, isn't 5G the n...
- 20 Apr 2020
PCB、IC封装：设计与仿真分析: 极致PCB设计全流程 I 技巧二：有效利用格点系统

SDA China

在PCB设计过程中，一些工具使用技巧的掌握，能够让我们的设计事半功倍。 “极致PCB设计全流程”——第二期技巧篇：“有效利用格点系统”将跟大家分享“env+快捷键设置+格点系统”的联合应用，不仅使设计更加便利、高效，还能确保PCB中相同模块的设计一致性。关注微信公众号“Cadence楷登PCB及封装资源中心”，在微信后台回复关键词“PCB全流程”即可...
- 19 Apr 2020
Breakfast Bytes: Sunday Brunch Video for 19th April 2020

Paul McLellan

www.youtube.com/watch Made in my living room (camera Carey Guo) Monday: John Park Webinar: Is It the Age of the Chiplet? Tuesday: The Furthest Man Has Been from Earth Wednesday: HiFi DSPs - Not Just for Music Anymore Thursday: Bringing Clarity o...
- 19 Apr 2020
Breakfast Bytes: It's a SLAM Dunk Programming the Vision Q7 DSP

Paul McLellan

The Tensilica Vision Q7 DSP is the sixth-generation vision and AI DSP. It has an enhanced instruction set and additional hardware for SLAM applications. Cadence has a SLAM library that is optimized for the Vision Q7 DSP and lets SLAM applications be...
- 17 Apr 2020
Analog/Custom Design: Start Your Engines: AMSD Flex—Take your Pick!

Qingyu Lin

Introduction to AMSD Flex mode and its benefits.
- 16 Apr 2020
Verification: Metamorphic Testing: The Future of Verification?

XTeam

Curious about what’s going on behind the scenes with verification? Bernard Murphy, Jim Hogan, and our own Paul Cunningham are on the case with the “Innovation in Verification” blog stream over at semiwiki.com. Every month, this trio reviews a newly-published paper in academia that pertains to verification and discusses its implications. Be sure to stop by—it’s a great place to see what might be coming…
- 16 Apr 2020
Digital Design: Library Characterization Tidbits: Rewind and Replay

Jommy

A recap of the blogs published in the Library Characterization Tidbits blog series.
- 16 Apr 2020
System, PCB, & Package Design : BoardSurfers: Five Easy Steps to Create Footprints Using Packages in Library Creator

Sanjiv Bhatia

In my previous blog, I talked about creating a footprint using an existing template in Allegro ECAD-MCAD Library Creator and explained how easily you can access an existing template and create a package from it by just clicking a button. In this blog...
- 16 Apr 2020
Breakfast Bytes: Bringing Clarity of Signal to High-Performance Connector Design

Paul McLellan

I recently wrote a white paper on Signal Integrity for 112G, which I'll post about once it is available for general download. I covered a broad range of Cadence technology from 112G SerDes design IP (DIP), to IBIS and AMI models for the channel, to ...
- 16 Apr 2020
Analog/Custom Design: Virtuosity: Concurrently Editing a Hierarchical Cellview

Sucharita

This blog discusses key features of concurrently editing a hierarchical cellview.
- 15 Apr 2020
Breakfast Bytes: HiFi DSPs - Not Just for Music Anymore

Paul McLellan

When the Tensilica HiFi DSP family was first created, the focus was all on low-power high-fidelity music. Hence the name of the product. I've written about this over the years: Dolby Atmos and Tensilica Movie Theater Sound in Your Phone So in that...
- 15 Apr 2020
Whiteboard Wednesdays: Whiteboard Wednesdays - TensorFlow to RTL with High-Level Synthesis

References4U

In this week’s Whiteboard Wednesdays video, Dave Apte explains the flow from a TensorFlow description of a machine-learning network to a high quality RTL implementation by leveraging Cadence’s Stratus HLS solution.

https://youtu.be/KXHL4i1WdXQ
- 14 Apr 2020
System, PCB, & Package Design : IC Packagers: Time-Saving Alternatives to Show Element

Tyler

In the Allegro back-end layout products like Allegro Package Designer Plus, it would be reasonable to assume that the most often used command is none other than “show element” (shortcut key F4). This command, runnable at nearly any t...
- 14 Apr 2020
Breakfast Bytes: The Furthest Man Has Been from Earth

Paul McLellan

What is the furthest that man has been from Earth? And who? If I tell you that today is the 50th anniversary of that event, then you will immediately realize that it must be the three astronauts who were on Apollo 13: Jim Lovell, Jack Swigert, and F...
- 14 Apr 2020
Analog/Custom Design: Virtuoso Meets Maxwell: Keeping Things Simple in the Virtuoso RF Solution

kfullerton

We have all heard the sayings “Less is more” and “Keep it simple”. Electromagnetic simulation is an activity where following that advice has enormous payoffs. In this blog I’ll talk about some of my experiences with how Virtuoso RF Solution’s shape simplification feature has helped my customers get significant performance improvements with minimal impacts on accuracy.
- 13 Apr 2020
Breakfast Bytes: John Park Webinar: Is It the Age of the Chiplet?

Paul McLellan

I first started paying attention to 3D packaging many years ago. Every year there was a conference at the Hyatt in Burlingame on the topic. Everyone was convinced that 3D packaging was coming really soon. Here is a Semiwiki post from 2014 that ...
- 13 Apr 2020
定制IC芯片设计 : Virtuosity：回顾2019年Virtuoso ADE Product Suite 及 Virtuoso Visualization and Analysis

shubhangi upadhyay

对于 Virtuoso®ADE Product Suite 和 Virtuoso® Visualization and Analysis 而言，2019 年是非常重要的一年。我们不仅添加了诸如多测试编辑器之类的新功能，而且还重新设计了一些现有表格，以为您提供最佳体验。可靠性设置，激励设置和多工艺仿真就是其中的几个例子。除此之外，我们还新添加了一些版图后仿真相关的增强功能! 今年的另一项重大更新是 Virtuoso®ADE Verifier 与 Cadenc...
- 13 Apr 2020
Breakfast Bytes: Sunday Brunch Video for 12th April 2020

Paul McLellan

www.youtube.com/watch Made on my balcony (camera Carey Guo) Monday: From Castles and Moats to Zero-Trust Networking Tuesday: The Dynamic Duo Wednesday: Online Support? There's an App for That! Thursday: Designing Chips for Hyperscale Da...
- 12 Apr 2020
PCB、IC封装：设计与仿真分析: 极致PCB设计全流程 I 基础二：DFx规则设定

SDA China

当布线过程中或者布线结束时，发现器件布局不合理，我们将进行繁琐的调整工作。对于复杂PCB，这个调整可能会占用我们整个上午的时间，甚至更久。如果设计者在布局开始时，设定了DFx的相关规则，那么这种问题出现的概率将大幅下降，有效提升设计质量和效率。 “极致PCB设计全流程”第二期基础篇“DFx规则设定”为您详细指导。关注微信公众号“Cadence楷登PCB及封装资源中心”，在微信后台回复关键词“PCB全流程&rd...
- 10 Apr 2020
Digital Design: Joules – Power Exploration Capabilities

Neha Joshi
Several tools can generate power reports based on libraries & stimulus. The issue is what's NEXT?

Is there any scope to improve power consumption of my design?

What is the best-case power?

Pin-point hot spots in my design?

How to recover wasted power?

And here is the solution in form of Joules RTL Power Exploration. Joules’ framework for power exploration and power implementation/recovery is stimulus based…
- 10 Apr 2020
Digital Design: Exploring Genus-Joules Integration is just a click away!!

Neha Joshi
Joules RTL Power Solution provides a cockpit for RTL designers to explore and optimize the power efficiency of their designs. But this capability is now not just limited to RTL designers!! Yes, you as a synthesis designer too can use the power analysis capabilities of Joules from within Genus Synthesis Solution!!

But:

How to do it?

Is there any specific switch required?

What is the flow/script when Joules is used from…
- 10 Apr 2020

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