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PCB、IC封装：设计与仿真分析: 年度网课：极致PCB设计全流程网课计划

SDA China

“工欲善其事，必先利其器”，我们要高质高效完成PCB设计，除了有效的规划及设计策略外，还必须深入理解工具的使用方法和设计技巧。只有夯实这些基础，我们才能真正避免“重复劳动”，提升设计质量和效率。娴熟的PCB设计者，可以将更多时间分配于传输线理论、SI/PI、电磁场等理论知识的研究，做更深层次的PCB设计。为了兼顾不同观众的需求，今年我们采用“理论知识 + 实战演示”，的方式，循序渐进地与大家在线分享PCB设计各个阶段的基...
- 21 Feb 2020
Digital Design: Library Characterization Tidbits: Over the Clouds and Beyond with Arm-Based Graviton and Cadence Liberate Trio

Seena Shankar

Cadence Liberate Trio Characterization Suite, ARM-based Graviton Processors, and Amazon Web Services (AWS) Cloud have joined forces to cater to the High-Performance Computing, Machine Learning/Artificial Intelligence, and Big Data Analytics sectors.
- 21 Feb 2020
Breakfast Bytes: DesignCon: Design for Security

Paul McLellan

At DesignCon, one of the keynotes was by Warren Savage titled Design for Security: The Next Frontier of Smart Silicon. I have known Warren for years—he has been in IP for a long time, most recently as CEO of IPextreme, which he founded in 2004 ...
- 21 Feb 2020
Analog/Custom Design: Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 1

Dishika Majumdar

This blog will take you on a short tour to the Cadence Education Services site, which has several online training courses and bytes based on specific features of Virtuoso products.
- 20 Feb 2020
Breakfast Bytes: Getting on to the Internet in 1993

Paul McLellan

I recently listened to an a16z podcast about crypto. It was an interview by Katie Haun with Marc Andreessen, the co-founder of Andreessen-Horowitz aka a16z. For me, the most fascinating part was not the crypto, but two aspects of the ...
- 20 Feb 2020
Breakfast Bytes: What If It's Not 5G, But Satellites?

Paul McLellan

What if the answer to next-generation communication is not 5G but space? Elon Musk apparently noticed that the margins of the companies for which Space X was launching satellites were better than Space X's own margins. So why not use those rocke...
- 19 Feb 2020
System, PCB, & Package Design : IC Packagers: An Introduction to Via Arrays

Tyler

Vias are present in every design (except maybe some lead frames and the very rare single-layer substrate). Where they are placed, and how many there are, will depend on a slew of factors, though, as we know. There are different situations and reasons...
- 18 Feb 2020
System, PCB, & Package Design : BoardSurfers: Training Insights - Improving SI/PI Simulation of DDR Interfaces at the PCB/IC Package Level

mrigashira

In the days of yore when life was simple, there was a world full of DRAMs (Dynamic Random Access Memory). We have come a long way from there. First came Synchronous DRAMs (SDRAMS). Isn't it neater anyway, SDRAM? More systematic and organized, in tune...
- 18 Feb 2020
The India Circuit: Playing for Good

Madhavi Rao

Last Saturday, Cadence and Concern India Foundation hosted a very special event - a charity sports tournament for corporates called “5Cs” – the Corporate Citizenship Challenge for the Cause of Children. It is one of the most fun eve...
- 18 Feb 2020
Breakfast Bytes: DVCon 2020 Preview

Paul McLellan

Coming up to the big conferences like DAC, I like to do one or more preview posts, both as a service for people who are already going to help them decide what to attend, and also to encourage people in the industry to attend. DVCon is another confere...
- 18 Feb 2020
Breakfast Bytes: Sunday Brunch Video for 16th February 2020

Paul McLellan

https://youtu.be/uc_vrZsq-2I Made in Cadence parking lot (camera Steve Brown) Monday: Benedict Evans 2020: Standing on the Shoulders of Giants Tuesday: Benedict Evans 2020: Regulating the Giants Wednesday: System Analysis: Computational Software...
- 16 Feb 2020
System, PCB, & Package Design : BoardSurfers: PCB Electronics—Why Use Via Arrays?

mrigashira

We all know the ubiquitous via. What is it after all but a way to make electrical connections in a multi-layered PCB? But if you think about it, it must have been a clever ....
- 14 Feb 2020
Breakfast Bytes: Quines on Valentine's

Paul McLellan

Monday is President's Day and Cadence is off so, as has become traditional, I write about something off-topic the day before. Today's topic is self-reproducing programs. A self-reproducing program is also known as a Quine. The term Quine was ...
- 14 Feb 2020
Analog/Custom Design: Virtuosity: Updated Virtuoso ADE Explorer and ADE Assembler RAKs in IC6.1.8/ICADVM18.1 ISR9

Arja H

To show the latest features in IC6.1.8/ICADVM18.1 ISR9, we've updated the Rapid Adoption Kits for Virtuoso ADE Assembler and Virtuoso ADE Explorer. In addition, we have updated the RAK that explains the Stimuli Assignment form.
- 13 Feb 2020
Breakfast Bytes: Under the Hood of Clarity and Celsius Solvers

Paul McLellan

Yesterday, in my post System Analysis: Computational Software at Scale, I talked about computational software at scale and the three aspects that Cadence is delivering: Algorithms that operate on unimaginably huge amounts of data Scaling algori...
- 13 Feb 2020
Breakfast Bytes: System Analysis: Computational Software at Scale

Paul McLellan

In about 2000, when I was the VP of Strategic Marketing for Cadence, I got a strange voicemail that started "This is Regis McKenna...". If you are old enough, you know that Regis, and his PR firm Regis McKenna Inc, was a legend in&nbsp...
- 12 Feb 2020
Academic Network: Third Annual RESCUE Winter Workshop

Marianne Paz

Cadence hosted the third annual RESCUE Winter Workshop from 14th to 22nd of November 2019, in Feldkirchen, Germany. The Winter Workshop is an annual event attended by the RESCUE participants. Cad...
- 11 Feb 2020
System, PCB, & Package Design : IC Packagers: RF Symbols, Coils, and Structures in IC Packages

Tyler

So, you need to add more complicated structures into your package design. What options do you have available to you in the Cadence packaging products with the 17.4 release – whether you’re using the base Allegro Package Designer Plus or h...
- 11 Feb 2020
Breakfast Bytes: Benedict Evans 2020: Regulating the Giants

Paul McLellan

This is the second post about Benedict Evans' annual big presentation about the internet. Part 1 appeared yesterday in my post Benedict Evans 2020: Standing on the Shoulders of Giants. Regulation We connected everyone... including the bad people....
- 11 Feb 2020
Verification: Verification of the Lane Adapter FSM of a USB4 Router Design Is Not Simple

Neelabh

Verifying lane adapter state machine in a router design is quite an involved task and needs verification from several aspects including that for its link training functionality.

The diagram below shows two lane adapters connected to each other and each going through the link training process. Each training sub-state transition is contingent on conditions for both transmission and reception of relevant ordered sets needed…
- 10 Feb 2020
Digital Design: Library Characterization Tidbits: Liberate MX for Memory Characterization Video Series

Jommy

As we embark upon our blogging journey again in 2020, in this Library Characterization Tidbits series, we want to draw your attention to an informative video series on memory characterization, which is available on the Cadence support portal.
- 10 Feb 2020
Breakfast Bytes: Benedict Evans 2020: Standing on the Shoulders of Giants

Paul McLellan

For the last five or six years, Benedict Evans worked at Andreesen-Horowitz (a16z) and would do a big presentation on the state and future of the internet at the end of each year. He recently left a16z to return to the UK (he's English) and so hi...
- 10 Feb 2020
Breakfast Bytes: Sunday Brunch Video for 9th February 2020

Paul McLellan

https://youtu.be/CVbxaO8cVoM Made in Steve's office (camera Steve Brown) Monday: Persistent Memory at Twitter Tuesday: How Technologies Get into EDA Wednesday: The Signal Integrity Story Thursday: Exadata: An Epic Journey at Oracle with Persisten...
- 9 Feb 2020
Academic Network: Certified TowerJazz-Cadence Analog Lab at KPI in Ukraine

Anton Klotz

Around one year ago TowerJazz VP, Ori Galzur, contacted us and suggested to start a collaboration with academia in Ukraine. TowerJazz is an Israeli-US foundry for analog circuits, mainly image sensors, automotive, silicon photonics and RF, with over ...
- 7 Feb 2020
Analog/Custom Design: Virtuosity: Blogging Journey of Virtuoso Place and Route in 2019

Parula

To support various new features and enhancements in Virtuoso Placement and Routing, our tech gurus and the writers collaborated to publish some informative blogs in 2019. This blog is a sneak peek into the blogging journey of Virtuoso Placement and Routing and provides you a handy summary to make it easy for you to read these blogs at your leisure.
- 7 Feb 2020

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