Find Other Members ►

Get email delivery of the Cadence blog (individual posts).

Community

Blogs
Forums
Resources

Latest Forum Posts

Visit the User Forums »

Latest Blog Posts

PCB、IC封装：设计与仿真分析: 专家访谈：多板PCB系统设计新思路

Sigrity

本文转载自Semiwiki.com。许多电子产品的创意都是从草图开始，然后在Visio或PowerPoint中绘制图表，最后再进入特定的EDA工具中进行设计。但是，这种方法使得纯图形工具绘制的图与EDA工具的设计之间存在很大的脱节，由于没有发生数据链接，所以在规范进行了更改后无法实现一致性和自动化。需求是前进的动力，Cadence® Allegro® System Capture工具可将对PCB系统级设计的需求转化为现实功能，不妨请 Cadence的Gary Hinde来为大家...
- 25 Oct 2019
Breakfast Bytes: The California DMV on Autonomous Cars

Paul McLellan

Earlier in the week I gave an overview of Silicon Valley Reinvents the Wheel. That was largely about the factors that would make autonomous vehicle manufacturers successful, and how accepting the general public are of the technology. But here in Cali...
- 25 Oct 2019
定制IC芯片设计 : Virtuosity：在Modgen中支持堆叠式设备

Aneesh Shastry

该博客概述了Modgen中对堆叠设备的支持。此功能使您可以轻松地在高度复杂的设计中可视化和编辑设备，从而有助于在高级节点PDKs中实现更高的电路性能目标。阅读博客文章，以了解有关如何在Modgen中使用堆叠式设备的更多信息。
- 24 Oct 2019
Life at Cadence: A Tale from Two Cities: Hear from Two Cadence Interns

Ashley Sneathen

Here at Cadence, we welcome students from universities around the world to any number of our 20+ campuses globally. Joining teams across all solutions and services throughout the company, these talented, helpful interns jump in to immediately work on...
- 24 Oct 2019
Breakfast Bytes: 40 Years Ago, "Spreadsheet" Didn't Mean Excel, It Meant VisiCalc

Paul McLellan

I like to find specific events that change the trajectory of the semiconductor industry, such as June 29, 2007, when the iPhone was announced. Today is the 40th anniversary of another such event. Forty years ago today, on October 24, 1979, Dan B...
- 24 Oct 2019
Breakfast Bytes: Silicon Valley Reinvents the Wheel

Paul McLellan

Recently the Western Automotive Journalists, or WAJ (I had no idea that was a thing), held their annual Silicon Valley Reinvents the Wheel event at the Computer History Museum in Mountain View. Outside in the parking lot was a broad selection of auto...
- 23 Oct 2019
Analog/Custom Design: Virtuoso Video Diary: Technology File Maintenance Made Easy

Uma Peethambaran

The Virtuoso Techfile IDE offers a powerful and modern interface to easily create and modify ASCII technology files.
- 23 Oct 2019
Analog/Custom Design: Virtuoso IC6.1.8 ISR7 and ICADVM18.1 ISR7 Now Available

Virtuoso Release Team

The IC6.1.8 ISR7 and ICADVM18.1 ISR7 production releases are now available for download.
- 22 Oct 2019
System, PCB, & Package Design : IC Packagers: Manage Your Outside Data Sources in One Place

Tyler

Every package design has data sources. Die data you receive from the IC design team as they send you updated die text files and co-design die abstracts. Your downstream PCB design team may send an updated ball map spreadsheet with change requests. Obviously, your front-end schematic engineer will be pushing you updated netlist information. How do you keep track of when the last time was that you imported data from a…
- 22 Oct 2019
Breakfast Bytes: Arm TechCon: A Look at 2020 and 2030

Paul McLellan

The last day of Arm TechCon opened with the return to the event of Charlie Miller. I already covered that in my post Charlie Miller: Stopping Cars Being Hacked Instead of Hacking Them. For my first post about Arm TechCon this year, see my post Arm Te...
- 22 Oct 2019
Analog/Custom Design: Virtuoso Meets Maxwell: Help With Electromagnetic Analysis - Part II

Kabir

This is the second blog in the multi-part series that aims at providing in-depth details of electromagnetic analysis in the Virtuoso RF solution. For some useful guidelines on selecting geometries for electromagnetic analysis, read
- 21 Oct 2019
Breakfast Bytes: EDPS 2019: Efficient Design and Manufacturing

Paul McLellan

EDPS, the Electronic Design Process Symposium, took place on October 3 and 4 at SEMI HQ in Milpitas. The theme was Efficient Design and Manufacturing. Camille Kokozaki The meeting opened with a moment of silence for Camille Kokozaki, who had helped ...
- 21 Oct 2019
PCB、IC封装：设计与仿真分析: 如何创建最佳PCB叠层

TeamAllegro

当进行装修时，我们会发现选择材料时最好要咨询专家或者有经验的人。举例来说，也许装修类杂志推荐了一种非常昂贵的屋顶材料，但是当我们到当地的家装店询问后，发现当地的气候根本不需要这种极其耐用坚固的材料，普通材料即可满足我们的需求。在电路板设计上创建PCB叠层也会遇到类似情况：我们可能不了解最适宜的PCB材料，也不知道如何有效地构建叠层。在作出决定之前，清楚了解我们的需求才能对设计最为有利。优化设计意味着梳理可供考虑和选择的众多变量。本文将讨论如何确定哪些PCB叠层信息需要了解的方式方法。 01....
- 18 Oct 2019
定制IC芯片设计 : Spectre 技术小窍门：器件老化？是的，即使是硅也会失效

Meilin Zhang

作者：Moustafa Moham 虽然我们大多数人都希望我们的电子产品永远工作，但事实是这些产品有生命周期。大多数情况下，器件的寿命受到机械（开关，继电器）或热（熔断器，电容器）故障的限制。然而，随着先进工艺设计的微芯片变得越来越常见，微芯片的寿命成为另一个问题。几种效应会导致器件老化。某些影响，如电迁移和Time-Dependent Dielectric Breakdown (TDDB)会导致突然故障，而其他影响，如Hot Carrier injection (HCI)和Bias Temp...
- 18 Oct 2019
定制IC芯片设计 : Spectre 技术小窍门：如何使用 Spectre APS 在 ADE 中执行 EMIR 分析？

Meilin Zhang

作者：Stefan Wuensche Spectre 技术小窍门是一个博客系列，旨在探索 Spectre® 的功能和潜力。除了深入了解 Spectre 的有用功能和优化改进之外，本系列还传播不同博主和专家的声音，他们将分享他们在与Spectre 相关的所有事情上的知识和经验。本系列的第一篇博客将指导您完成使用 Spectre APS 在 ADE 中执行 EMIR 分析所需的步骤。作为模拟或混合信号设计人员，您将在Virtuoso® Analog Design Environme...
- 18 Oct 2019
Breakfast Bytes: Book: VLSI Design Methodology Development

Paul McLellan

There are lots of books on EDA, but many of them are academic texts about the algorithms used inside EDA tools. Rather fewer of them are written for people doing real designs. A recently published book firmly targeted at the practical needs of ...
- 18 Oct 2019
Analog/Custom Design: Virtuosity Webinar: Achieving Layout Success with Custom Design Planner and Design Intent - October 29, 2019

sarahfino

Enhance productivity with Design Planner and Design Intent. Attend our FREE one-hour webinar with Baby Ravi and Bill Cambouris on Tuesday, 29 October 2019.
- 18 Oct 2019
SoC and IP: Did You “Stress Test” Yet? Essential Step to Ensure a Quality PCIe 4.0 Product

William Chen

The PCI-SIG finalized the PCIe 4.0 specification with doubling the data to 16GT/s from 8GT/s in PCIe 3.0 in 2017. Products implementing this technology have begun to hit the market in 2019. Earlier this year, AMD announced it X570 chipset would support the PCIe 4.0 interface and Phison also introduced the world’s first PCIe 4.0 SSD. With the increasing companies are working on PCIe 4.0 related product development…
- 17 Oct 2019
Breakfast Bytes: Samsung: In SAFE Hands

Paul McLellan

Today is Samsung's SAFE Forum 2019 at their Samsung@First building on San Jose's First Street. SAFE stands for Samsung Advanced Foundry Ecosystem. Since Samsung Foundry really only has two events per year, the other being the Samsung F...
- 17 Oct 2019
Life at Cadence: Taking the Trip of a Lifetime

TramN

This year, I was excited to be one of 10 Cadence employees selected from 130 applicants to participate in the company’s first international volunteer service immersion program with the nonprofit Team4Tech. The team was brought together to work ...
- 16 Oct 2019
Breakfast Bytes: Charlie Miller: Stopping Cars Being Hacked Instead of Hacking Them

Paul McLellan

The last day of Arm TechCon opened with Charlie Miller talking about Experiences with and Views on the Future of Driverless Cars Technology. Charlie has appeared in Breakfast Bytes before in Automotive Security: A Hacker's Eye View. He, alon...
- 16 Oct 2019
Analog/Custom Design: Virtuoso Video Diary: Record. Replay. Relax.

Pallabi R

Want to record your work and replay it later? Want to automate things and save time? Then start using the "Record and Replay Files" available in Virtuoso Abstract Generator.
- 16 Oct 2019
Whiteboard Wednesdays: Whiteboard Wednesdays – Verification with Emerging Memory Models

References4U

In this week's Whiteboard Wednesdays video, David Peña discusses Cadence’s focus on models for various emerging memory standards.

https://youtu.be/_Xps6I6kE0E
- 15 Oct 2019
SoC and IP: PCIe 3.0 Still Shines While PCIe Keeps Evolving

William Chen

PCIe has been widely adopted in the electronics industry since its first debut in 2003 (PCIe 1.0 standard release) for wide breach of applications, from Data Center Server, Networking, to Mobile, AI/ML, Automotive, IoT, and many others…. It’s a versatile, high-performance, robust, mature interconnect standard with full “backward compatibility” (e.g., a PCIe 3.0 device can still function well in a PCIe 4.0 system) which…
- 15 Oct 2019
System, PCB, & Package Design : IC Packagers: Optimize Display Settings for Faster Screen Redraws

Tyler

While designing interposers and very high pin count device packages, as the number of objects to manipulate increases, you may notice that the display takes longer to draw. This is for a very good reason: by default, the tools will draw everything.....
- 15 Oct 2019

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.