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In this week's Whiteboard Wednesdays video, Chris Rowen discusses optimizing neural networks for low-energy and high-throughput applications.

https://youtu.be/AY2944-dyr8

This year’s CDNLive Silicon Valley developer conference had more than 125 presentations from 12 different technical tracks. More than 25 exhibitors participated in the Designer Expo.

The IC Packaging/Signal Integrity/Power Integrity track featured customer papers on co-design as well as signal, power, and thermal integrity. With the challenge of creating final products as quickly and as efficiently as possible…

Pieter Vorenkamp is the new(ish) senior VP and general manager of the semiconductor IP group here at Cadence. With both of us traveling a lot last month, it took about a dozen attempts to find a slot when we could talk, but the only slot was on my way...

If you were asked where in the world the most leading-edge semiconductor research is done, you'd probably pick the US or perhaps Taiwan. But the real answer is Belgium. Not even Brussels, but Leuven, a small town about 15 miles to the east where imec...

At the recent GSA silicon summit, there was a panel session on designing for the cloud. The panel was moderated by Linley Gewennap of the Linley Group. The panelists were Ivo Bolsoens, the CTO of Xilinx, Ian Ferguson from ARM, and Stephen Pawlowski of...

In this week's Whiteboard Wednesdays video, Arif Kahn details the evolution of the USB interface from USB 1.0 to today's latest USB Type-C interface.

https://youtu.be/x4RFNG1vdWs

It is hard to attend any sort of meeting to do with semiconductors without hearing about the Internet of Things (IoT), and probably the hottest subtopic is IoT security. Some devices will contain our health data, some are dangerous. Even the apocryphal...

This month, we celebrate the 20^th anniversary of Specman’s introduction to the public—at DAC 1996 in Las Vegas. This introduction was not simply of a new tool—it was the introduction of a new concept. Specman included e, and thus, with that introduction, the first Hardware Verification Language was born.

Many of you, I suspect, were still in high school in the 1990s. You would be amazed if you saw some…

IEEE European Test Symposium (ETS) is the largest event in Europe committed to presenting and discussing scientific trends, emerging results, hot topics and applications in the area of electronic-based circuits and system testing. ETS’16 which took place...

Back in May, Professor Gilles Jacquemod and 9  engineering students from Tianjin University who are currently visiting Sophia-Antipolis engineering school stopped by the Cadence office in Sophia, France.The students have been selected to participate in...

One of the keynotes at the imec technology forum last month was by Gary Patton, the CTO of GLOBALFOUNDRIES. I reminded him in the evening event at the Magritte museum that he'd done an interview with me last year that had gone viral inside GLOBALFOUNDRIES...

Neural networks have become very popular today due to their use in leading-edge technology like deep learning machines, artificial intelligence, and virtual reality. Neural networks offer a powerful way to extract meaning in recognizing objects and actions within a visual stream. It's a topic with a lot of buzz today, and as the use of it becomes more and more pervasive, it’s just a matter of time before the devices we…

PCI-SIG is a leading event in cloud infrastructure transformation, which is markets all over the world. We see a lot of market forces at work, creating urgency for PCIe Gen4 dynamics. Designers, system architects, engineers and engineering managers will be the driving force behind another PCI-SIG event. Taking place on June 28-29 2016 at the Santa Clara Convention Center, California, this prestigious event is filled with…

CDNLive EMEA is often cited as the most exciting event of the year for Cadence. This being the first time I would be attending any CDNLive, I was eager to see for myself if this was true and I must say in retrospect, that all my expectations were met...

I was in Brussels a couple of weeks ago to attend imec's annual technology forum. One of the keynotes on the first morning was from Wally Rhines, Mentor's CEO, entitled Extending Semiconductor Cost Reduction Another 20 Years. As Gordon Moore himself...

I had never heard of the RISC-V (pronounced five, not vee) instruction set until earlier this year when there was a presentation about it at EDPS in Monterey. I immediately texted the daughter of a friend of mine who is a CS major at Berkeley where it...

Another DAC, and this year someone put a jalapeno in my margarita at the Denali Party. The burn came on slow, and was merciless. So we all yelled “Carpe Diem!”

The really good news is that there was a lot of traffic at the floor show, and we seemed to garner the largest crowds. Overall attendance was strong. And we saw increased interest in customers talking with our IP technical experts at the Expert Bar…

Wouldn't it be great if you could see your plots directly on the schematic? Well in ADE Explorer, now you can!

Run a simulation in Explorer and open the design in tab and choose Waveforms from the show/hide balloon drop down or use the bind key CTRL+B

Hover over the nets/terminals in the design and balloons showing the simulation plot will appear.

To pin the balloons use the bindkey SHIFT+B or click on…

The Raspberry Pi has firmly established itself as a household name by providing a hands-on way to learn programming in a small, simple, and very affordable package. First released just over 4 years ago in February 2012, the device can not only handle...

At DAC, Cadence had their now traditional verification lunch. Brian Fuller returned in his role as the host and moderator. The panel consisted of:

• Jim Hogan of Vista Ventures, another Cadence alumnus, and an expert on the EDA industry in general (and...

On 21 April, Cadence and the Moscow Institute for Electronics Technologies (MIET) organized Technology Days in the MIET building in Zelenograd in the vincinity of Moscow. Zelenograd is the heart of the Russian microelectronics industry—both Russian foundries...

Cadence Academic Network is a worldwide activity; therefore, the team members are often traveling to quite exotic places on earth to visit universities, talk with the professors, and tell them what Academic Network can offer them. One of the most...

The 16.6-2015 Allegro PCB Editor release introduces the interactive conversion of Orthogonal and 45-degree routed traces into a Zig-Zag pattern to minimize the Fiber Weave Effect in a Printed Circuit Board (PCB).

What is “Fiber Weave Effect”?...

From May 2 to May 4, Cadence once again hosted their hugely popular user conference CDNLive EMEA. The Academic Track, co-ordinated by the Cadence Academic Network, is a platform to share papers about advances in teaching methods and research techniques...

For all IP providers, the ultimate proof of quality of their product is certification for standard compliance. Exhaustive testing conducted by third-party labs or at compliance workshops assess the behavior of the component across variety of conditions that can take place in customer’s application. Passing the compliance suite helps both convince existing prospects, as well as promote to get new ones.

Cadence has…