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Verification: DAC 2019 Preview – Multi-MHz Prototyping for Billion Gate Designs, AI, ML, 5G, Safety, Security and More

fschirrmeister

Vegas, here we come. All of us fun EDA engineers at once. Be prepared, next week’s Design Automation Conference will be busy! The trends I had outlined after last DAC in 2018—system design, cloud, and machine learning—have...
- 29 May 2019
Analog/Custom Design: Spectre Tech Tips: Spectre APS Save Overview - Part 1

Stefan Wuensche

As an analog/mixed-signal designer, verification engineer, or CAD expert, you use Spectre® APS for analyzing your designs. Saving node voltages, element, and subcircuit port currents and power is an essential part when simulating your designs. Over the years, incremental additions to the Spectre waveform writing functionality have made it more complex. In SPECTRE17.1 ISR15, and SPECTRE18.1 ISR7 releases, we’ve consolidated…
- 29 May 2019
Breakfast Bytes: Verific, 20 Years Terrific

Paul McLellan

What do JasperGold, Stratus, and the Rocketick part of Xcelium have in common? Well, they are all Cadence products, of course. But they also all use Verific as parsers for SystemVerilog, Verilog, and VHDL. Verific got started twenty years ago, Rob De...
- 29 May 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Deep Dive on Simultaneous Localization and Mapping (SLAM) – Part 1

References4U

In this week’s Whiteboard Wednesdays video, Amol Borkar explains how SLAM works. From the creation of a map of an unknown environment and understanding the orientation of a camera in this space. Then he talks about the importance and the applications of SLAM. Finally, Amol talks about the building blocks of a SLAM flow. Must watch!

www.youtube.com/watch
- 28 May 2019
Verification: Thinci Finds Success with the Cadence Verification Suite

XTeam

On May 23rd, 2019, Cadence announced that Thinci has elected to use the complete Cadence Verification Suite to speed up the verification of their machine-learning and AI designs. Now, Thinci can access the new technologies available through the Cadence Verification Suite to shorten their product development time by months while improving verification coverage.

“We selected the Cadence Verification Suite because it enables…
- 28 May 2019
The India Circuit: Is The Gig Economy Is Here To Stay?

Madhavi Rao

While the term "gig economy" has been around a long time, it has gained traction in India only since around 2014 when Indian gig economy companies that hire a part-time workforce, such as Swiggy and Zomato (food delivery), Dunzo (delivery s...
- 28 May 2019
Breakfast Bytes: Protium X1: FPGA Prototyping for the Enterprise

Paul McLellan

Today Cadence announced the new Protium X1 Enterprise Prototyping Platform. The previous version, the Protium S1 Desktop Prototyping Platform, was the size of a small refrigerator and intended to be beside an engineer's desk. The Protium X1 platform,...
- 28 May 2019
System, PCB, & Package Design : IC Packagers: When Being Two-Sided is a Good Thing

Tyler

With each new generation, demand for smaller, faster, lighter, more efficient is at the top of the requirements list for most things. But, we cannot make things smaller forever. Instead, we need to look for more creative solutions. Where can we ...
- 28 May 2019
Breakfast Bytes: Sunday Brunch Video for 26th May 2019

Paul McLellan

https://youtu.be/mx1i55BxSTU Made at Cadence campus (camera Sean) Monday: Alberto and the Origins of the EDA Industry Tuesday: Samsung's 3nm GAA Process Wednesday: I/O Is Faster Than the CPU—What Now? Thursday: GOMAC: Software Is...
- 26 May 2019
System, PCB, & Package Design : BoardSurfers - Aerials and Bails: Minimum Screen Resolutions and Large Forms

Tyler

The Cadence® Allegro® backend layout tools are large, complex, highly-capable environments that provide you with a massive amount of functionality. Whether you are designing a rigid-flex PCB, a BGA package, an interposer, or something else entirely, they provide the features you need to accomplish the task.

However, with great functionality comes great… big forms, at times. Some of the largest forms in Allegro…
- 25 May 2019
PCB、IC封装：设计与仿真分析: 邀请函：2019 Cadence中国技术巡回研讨会

SDA China

诚邀您参加 “ 2019年度Cadence中国技术巡回研讨会”，会议将集聚Cadence的技术用户、开发者与Cadence资深技术专家，涵盖最完整的先进技术交流平台，从SoC设计、验证仿真到封装和板级设计的全流程的技术分享，您将有机会和开发Cadence工具的技术专家们面对面的直接沟通。 6月伊始，Cadence与您相约西安、成都、上海、深圳、北京！ space 会议为免费参加，座位有限，报名从速！会议咨询： event_cn@cadence.com 扫描下列二维码...
- 24 May 2019
Breakfast Bytes: Off-Topic: Syllepsis and Zeugma

Paul McLellan

It's Memorial Day in the US on Monday, and Cadence is off. So today is the day before a holiday. By tradition, I write about...whatever I feel like. So let's go with figures of speech. Even before I became a professional writer, I had a fasci...
- 24 May 2019
System, PCB, & Package Design : How to Model and Simulate 112Gbps PAM4 SerDes Using IBIS-AMI

Sigrity

With the buildout of 5G wireless networks and the constant demand for bandwidth in cloud-based data centers, serial link data rates continue to skyrocket. The current state-of-the-art serial links use 112Gbps data rates, using PAM4 signaling. PAM4 di...
- 23 May 2019
Breakfast Bytes: GOMAC: Software Is Never Done

Paul McLellan

When I was at GOMAC in Albuquerque at the end of March, I ran into a couple of Cadence people and a couple of Green Hills people. Everyone left except one of the Green Hills guys, since he was staying in a different hotel. He turned out to be John Wa...
- 23 May 2019
Breakfast Bytes: I/O Is Faster than the CPU—What Now?

Paul McLellan

At his keynote at CDNLive Silicon Valley, Andy Bechtolsheim made a throwaway remark that 1600G Ethernet would be a problem since "the packet rate is just 333 picoseconds so that needs wide Ethernet ports" (see my post Andy Bechtolsheim...
- 22 May 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - The 4 Steps Necessary for an Effective Cloud-Based Design Strategy

References4U

In this week's Whiteboard Wednesdays video, Craig Johnson identifies the 4 steps to follow to create an effective strategy for moving electronic design work to the cloud. Skip one of these and your results could be disappointing.

https://youtu.be/rKoatyYa35E
- 21 May 2019
Analog/Custom Design: Virtuoso Video Diary: Comparing Multiple Tests and Sharing Settings

Yuan Li

Have you been in the situation where you want to change a particular simulation setting in several of your tests in Virtuoso ADE Assembler? This can be a tedious process as you have to figure out which tests have that setting and what it is set to, then you have to go in to each test in turn to change it. From IC6.1.8 ISR3/ICADVM18.1 ISR3, we have added a tool to do just that. You can compare all the simulator settings…
- 21 May 2019
System, PCB, & Package Design : IC Packagers: Expanding Your (Thermal) Repertoire

Tyler

The process of attaching a component to your package substrate involves many factors, including heat. What happens whenever heat is applied to something? Expansion, of course! How much your die expands during the assembly process will be influenced b...
- 21 May 2019
Breakfast Bytes: Samsung's 3nm GAA Process

Paul McLellan

At the recent Samsung Foundry Forum, HK Kang, the EVP of semiconductor R&D, took to the stage. He's in charge of advanced logic, DRAM, 3D NAND, mask. But that day he was just going to talk about Samsung's 3nm gate-all-around (GAA) technol...
- 21 May 2019
Breakfast Bytes: Alberto and the Origins of the EDA Industry

Paul McLellan

At the 2019 International Symposium of Physical Design, the conference honored Alberto Sangiovanni-Vincentelli with a lifetime achievement award. Alberto was one of the cofounders of SDA Systems, the forerunner of Cadence, so in some ways he's a foun...
- 20 May 2019
Breakfast Bytes: Sunday Brunch Video for 19th May 2019

Paul McLellan

https://youtu.be/cTEPUNpqcRg Made at Samsung HQ (camera Sean) Monday: Bob Smith on ESD Alliance, ES Design West...with Wine Tuesday: After Meltdown and Spectre Wednesday: Vision Q7 DSP: Real-Time Vision and AI at the Edge Thursday: Samsung ...
- 19 May 2019
PCB、IC封装：设计与仿真分析: 汽车以太网应用的SI分析技术

Sigrity

现今汽车中车载电子设备的爆炸式增长，正在迅速改变向汽车消费者圆满提供高性能、可靠功能所需的工具和方法。汽车印刷电路板（PCB）的设计传统上一直由几个简单的器件互连组成、使用2层PCB，主要考虑的是成本问题。但是随着先进驾驶员辅助系统（ADAS）的普及，现在汽车可以包含多达100个电子控制模块（ECU），通过多线缆电缆束与安装在汽车四周的传感器相连。为适应传感器、数字逻辑与ECU之间更高性能的传输，汽车中所用部件之间的信号传输也在发生变化。目前大多数汽车采用的设计标准是100BASE-T1网络...
- 17 May 2019
Academic Network: CDNLive EMEA 2019, Impressions from the Academic Track

Anton Klotz

CDNLive EMEA 2019 was held May 6-8 in Munich, Germany. Bayern Munich did not qualify for the Champions League this year, so we were completely undisturbed and could listen to presentations, visit the exhibition, explore new ideas on collaboration and...
- 17 May 2019
Breakfast Bytes: Top 10 Reasons to Go to DAC

Paul McLellan

The Design Automation Conference is coming up soon. It's in Las Vegas from June 2 to 6 in the Las Vegas Convention Center (LVCC). Rob Aitken I was putting together a post on what I thought were good reasons to attend, but I decided to c...
- 17 May 2019
System, PCB, & Package Design : IC Packagers: Create Daisy Chain Substrates in a Flash with Cadence SiP Layout

Tyler

How do you go about testing your IC or package substrate when it comes to physical endurance? For many of us, a daisy chain test package is a common option. With practical uses including extreme environmental and temperature testing scenarios, a dais...
- 16 May 2019

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