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Artificial intelligence is rapidly expanding its reach into embedded systems and edge devices, driving the need for specialized processors that can efficiently handle complex AI workloads. While Neural Processing Units (NPUs) excel at accelerating neural network computations, the increasing demands of agentic and physical AI networks require a more comprehensive approach. This is where the Cadence Tensilica NeuroEdge…

If you missed joining or registering for the Boost Your Layout Productivity with Virtuoso Studio webinar, the complete recording is now available as a Training Byte at the Cadence support site.

This webinar will show you how to keep up with ever-changing layout requirements and challenges. We’ll also demonstrate Virtuoso Layout Suite capabilities that boost layout designer productivity in Virtuoso Studio, such as:…

3D heterogeneous integration (3DHI) technology creates high-performance systems by integrating different types of semiconductor chips or chiplets stacked vertically. Diverse functions such as processing, memory, and RF can thus be combined onto a single chip or package to improve performance and efficiency. As 3DHI systems increase in complexity, the importance of the Universal Chiplet Interconnect Express (UCIe) standard…

If you missed joining or registering for the Quantus Insight webinar, the complete recording is now available as a Training Byte at the Cadence ASK portal.

Running inside the Virtuoso Platform, the Quantus Insight Solution offers unique capabilities to analyse and mitigate layout parasitics in custom layout design. Particularly at advanced nodes, interconnect RCs can strongly affect design performance and power.

Engineered…

In the fast-paced world of analog and mixed-signal design, ensuring that your circuits meet stringent specifications is crucial. Enter Virtuoso ADE Verifier, a powerful tool designed to streamline and enhance the verification process for analog circuits. Whether you're an analog designer, verification lead, or project manager, Virtuoso ADE Verifier offers a comprehensive solution to meet your verification needs. It’s a…

On April 25, the UALink Consortium officially released the UALink 200G 1.0 Specification, marking an important milestone with support from key hyperscaler market players. It enables a low-latency, high-bandwidth fabric that supports hundreds of accelerators in a pod and facilitates simple load-and-store semantics.

The rapid evolution of Artificial Intelligence (AI) and Machine Learning (ML) is…

RAVEL, which stands for Relational Algebra Verification Expression Language, is designed for implementing system-in-package design rules. It builds on a relational view of the design data and is declarative in nature. RAVEL enables programmers to create new rules for the Allegro X PCB Editor and Allegro X Advanced Package Designer (APD) databases.

The updated online course for the RAVEL programming language introduces…