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RF /マイクロ波設計: μWaveRiders:RF /マイクロ波の学生様向けCadence AWRの大学プログラム

RF Design Japan

　Team RF "μWaveRiders" ブログシリーズがCadence AWR RF製品のためのショーケースとしてデビューします。月ごとの話題はCadence AWR Design Environmentのリリースのハイライト, 機能ビデオ, Cadenceの教育関係ネットワークのニュース,ソフトウェアのヒント, トリック, カスタマイズ, 機能のスポットライトの中で変わります。このシリーズの新しいブログに関する通知を受け取るために、Subscrib...
- 17 Mar 2021
RF Engineering: μWaveRiders: Cadence AWR University Program for RF/Microwave Students

TeamAWR

For students in the RF/Microwave area of study, the Cadence AWR Design Environment platform provides a range of tools that are extremely useful for many tasks, ranging from theoretical concept verification to advanced design capabilities covering the entire industry. The AWR academic license bundle includes an impressive list of capabilities via various tools integrated into a single platform.
- 17 Mar 2021
Computational Fluid Dynamics: ETNZ Wins the America's Cup Once Again Using FINE/Marine

Paul McLellan

Once again Emirates Team New Zealand has entered the history books and won the America’s Cup for New Zealand for the fourth time. After four years of planning and development, 170 years of Cup history, the last races of this 36th edi...
- 17 Mar 2021
Breakfast Bytes: DeepChip Best of 2020: vManager

Paul McLellan

We just finished 2020 (and let's hope 2021 is a better year). Every year, John Cooley runs a "best of EDA" survey, in which users vote on the best EDA products. This year, #2a on John's list is Cadence's vManager Verification Management. John announc...
- 17 Mar 2021
カスタムIC／ミックスシグナル: Virtuoso Meets Maxwell: Virtuoso RF ソリューション — フローの革命が次のレベルへ突入

Custom IC Japan

'Virtuoso Meets Maxwell' はVirtuoso RFソリューションとVirtuoso MultiTechの機能及びその潜在能力の紹介を目的としたブログの連載です。ではどのようにVirtuosoがMaxwellと出会うのでしょうか。現在、VirtuosoプラットフォームはRF設計をサポートしており、RF設計者は物理的な放射の影響をマクスウェルの方程式で測ります。この連載では、有益なソフトウェアの改善点にスポットを当てて解説するだけでなく、VirtuosoのIC...
- 16 Mar 2021
Analog/Custom Design: Virtuoso Meets Maxwell: How to Simulate an RF Block with Passive and Active Devices in EMX Planar 3D Solver?

jgrad

Do you work with RF designs that contain both active and passive devices? Have you been running electromagnetic simulations for those designs by making a copy of the design and removing active devices? So you have not explored the advanced full-cellview extraction feature yet. Read this blog to know more..
- 16 Mar 2021
Breakfast Bytes: Announcing Sigrity X

Paul McLellan

There are many different computational software algorithms used in EDA. One challenge of EDA is that design groups are always creating the next generation of SoCs on the current generation of processors. In the 1990s and 2000s, however, the microproc...
- 16 Mar 2021
RF /マイクロ波設計: AWR製品の技術サポートがCadence Online Supportに移行されました!

RF Design Japan

2021年3月8日以降、AWR製品の技術サポートは標準のケイデンスサポートプロセスに移行されました。このページは、この移行を通じてAWR製品のお客様を支援するトピックのコレクションです。ケイデンスオンラインサポートシステムを紹介するこの短いビデオをご覧ください。Cadence Online Support この変更の詳細は、AWRのナリッジベースのここで確認できます。また、日本語の書類もいくつか用意しました。ケイデンスオンラインシステムに登録する方法。希...
- 16 Mar 2021
定制IC芯片设计 : Virtuoso Meets Maxwell：跨结构电磁提取功能- 简化IC、封装和电路板耦合的任务

jgrad

当您在设计RFICs或RF模块时，如果只分析IC或模块上的电磁行为，那么可能会造成结果缺失。即使IC的电磁行为已达到其规格要求，也很容易将其耦合至模块周边的走线上，从而影响我们的判断。因此，只有IC和模块组合而成的电磁模型才能确保我们的系统按预期运行。通常对于我们说，组装IC 和封装几何形状是非常繁琐且容易出错的。我们必须手动从各个不同的平台调取数据，并且将其组装成3D模型。甚至有时每次设计迭代时，我们还需要手动重复这些步骤。.
- 15 Mar 2021
Breakfast Bytes: The History of PCIe: Getting to Version 6

Paul McLellan

PCIe, or Peripheral Component Interconnect Express which nobody ever says, was an upgrade to the earlier PCI bus. This was developed by Intel and introduced in 1992. It replaced several older, slower buses that had been used in a somewhat ad-hoc fash...
- 15 Mar 2021
Breakfast Bytes: Sunday Brunch Video for 14th March 2021

Paul McLellan

https://youtu.be/bzgotynPvs8 Made at Fry's Electronics in San Jose (camera Ziyue Zhang) Monday: Your Best Buys Are Always at Fry's Tuesday: Let’s Talk About Chiplets, Baby Wednesday: Paul Cunningham's DVCon Keynote: Verification Throu...
- 14 Mar 2021
Academic Network: Expanding Our Network — AWR Academic Partners

Kira Jones

We want to continue highlighting the amazing AWR academic connections! We’ll be covering the relationship with the University of Bristol and their many professor contacts, but specifically Professor Francesco Fornetti. We are also excited to a...
- 12 Mar 2021
RF Engineering: TECHTALK Webinar: Fast MMIC Design with Distributed EM Analysis

TeamAWR

Join us March 24th, 2021 at 11:00am - 12:00pm PDT for this webinar with Nick Chopra, CTO of Recon-RF, developers of custom MMICs and RF modules, to hear how his team uses the distributed EM analysis option in Cadence RF solutions to accelerate product development and improve high-frequency amplifier performance.
- 12 Mar 2021
Analog/Custom Design: Start Your Engines: Win Le Mans with the SimVision Mixed-Signal Debug Option

Andre Baguenie

In this post, I will explain how the new Cadence SimVision Mixed-Signal Debug option can reveal the Invisible portions of an Analog and Mixed-Signal Test Benches.
- 12 Mar 2021
The India Circuit: Saurav Bhardwaj: A Story of Resilience and Willpower

Asim Khan

Subsequent to my previous blog about the Cadence Scholarship Program, I bring to you another inspiring story featuring one of our students - Saurav Bhardwaj. Saurav's journey has been nothing short of remarkable. In 2016, he went through a dispir...
- 12 Mar 2021
Breakfast Bytes: The Carrington Event: When Will We Have Another?

Paul McLellan

Back in the pre-Cadence days when I had the EDAgraffiti blog, I wrote about the Carrington event. I got a lot of positive feedback about it from people in the electronics industry, mostly saying that they had never heard of it. The Car...
- 12 Mar 2021
Verification: Transport Layer – The Backbone of a USB4 Router

Neelabh

It won’t be incorrect to say that the transport layer of a USB4 router is the backbone of it. It is a layer that holds all the various other layers together. It provides the very essential services like paths and routing for tunneled traffic, various types of flow control, link management, which are some of the core features that make a USB4 router work the way it should.

A path is like a virtual wire, which is…
- 11 Mar 2021
Breakfast Bytes: Best of CadenceLIVE 2020: The Keynotes

Paul McLellan

The first CadenceLIVE 2021 will be CadenceLIVE Americas on June 8-9. It will be a digital experience. The call for presentations is already open—submit an abstract on this page before it closes on March 24. Also, registration has just opened. I...
- 11 Mar 2021
Analog/Custom Design: Virtuoso Video Diary: Knowledge Booster Training Bytes - Part 6

Parula

In this blog. we would like to let you know the information on how to achieve complete full-chip DRC signoff on advanced-node designs and efficiently run multiple DRC signoff iterations.
- 10 Mar 2021
System, PCB, & Package Design : Designing the Allegro System Capture Way

Rachna2018

A design starts in the mind of an architect, gets drawn on whiteboards as basic block diagrams that describe a system. Next, designers see what can be reused from older designs, schematics get drawn, parts are identified, from in-house libraries or from online vendors. If the available parts don’t match their requirement, librarians are asked to create or modify parts. Then checks and rules are run to ensure design integrity…
- 10 Mar 2021
Breakfast Bytes: Paul Cunningham's DVCon Keynote: Verification Throughput = Engines × Logistics

Paul McLellan

At DVCon 2021, the keynote was presented by Cadence's Paul Cunningham who is basically Cadence's Mr. Verification (officially he is Corporate VP and General Manager of System & Verification Group). He titled his presentation Computation...
- 10 Mar 2021
Digital Design: Voltus Voice: Demystifying ESD — Four Simple Steps to Run ESD Analysis Full-Chip Flow

Vijetha

This blog post outlines four simple steps for analysis of your electrostatic discharge (ESD) protection circuitry using the Voltus ESD Analysis solution.
- 9 Mar 2021
Academic Network: One-Stop Pages on support.cadence.com

Anton Klotz

This is intended for active users of Cadence Learning and Support. If you’re not a user yet, it’s easy to start! All academic users of Cadence software have the opportunity to access the support page. Students, please contact your profess...
- 9 Mar 2021
Breakfast Bytes: Let’s Talk About Chiplets, Baby

Paul McLellan

At CadenceLIVE Americas 2020, one of the most viewed videos was by Samsung Foundry's Kevin Yee and Cadence's Tom Wong. Despite the title of this blog post, the title of their presentation was a bit longer: Let’s Talk About Chips (Chiplets), Bab...
- 9 Mar 2021
Analog/Custom Design: Virtuoso Meets Maxwell: EMX—Industry-Leading EM Solver for RFICs

scottd

Hi all, this is my first blog for the Virtuoso Meets Maxwell series. It builds on the Virtuoso Meets Maxwell 2021 introduction blog. Today I get to discuss one of my favorite topics, electromagnetic (EM) analysis of RFICs using Cadence EMX Planar 3D Solver.
- 8 Mar 2021

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