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Spotlight Taiwan: Snapshots of CDNLive Taiwan 2018

candyyu

Taiwan is one of the most important hubs for the global semiconductor industry. Served as an annual important event for Cadence in Taiwan, with the efforts to provide tailored lineups for local industry, this year’s CDNLive Taiwan has suc...
- 11 Oct 2018
PCB、IC封装：设计与仿真分析: 升级到Allegro17.2-2016的10大理由之7：梯形凸块布线——下一代高速布线解决方案

TeamAllegro

通过梯形凸块布线高效利用布线通道梯形凸块布线是一种新方法，可以通过在并行走线上添加梯形形状来控制引脚区域或者突破区域的阻抗，减少开放区域的串扰。这是一个突破性的布线策略，可应对更长、更密的布线。（点击查看大图）不幸的是，这一新的布线技术增加了PCB设计的复杂度，在后续的设计流程中管理这些梯形凸块也很痛苦。我们听到了你们的求助，PCB layout工程师欢欣鼓舞！除了提供生成梯形凸块的方法，我们覆盖了梯形凸块的整个“生命周期”，几大特性如下：生成梯...
- 11 Oct 2018
Breakfast Bytes: ESD Alliance Workshop on Digital Marketing: Agility

Paul McLellan

Last week the ESD Alliance ran another workshop on digital marketing, with Nicolas Athanasopoulos of OneSpin and Dave Kelf (now at Breker, but who used to work with Nicolas at OneSpin). Unfortunately, they picked the same day as TSMC's OIP sympos...
- 11 Oct 2018
SoC and IP: NXP Introduces Tensilica HiFi 4 DSP-based Platforms to Secure IoT Edge Devices

PaulaJones

Trust. Privacy. Confidentiality. These are three important concerns for designers of IoT edge devices. Today NXP announced that they are addressing these concerns with two new platforms that feature secure execution environment (SEE) to give developers access to “unprecedented” security capabilities.

These platforms provide a multi-layered, hardware-enabled protection scheme to secure IoT edge devices and…
- 10 Oct 2018
Breakfast Bytes: Azure for Silicon Design with Cadence and TSMC

Paul McLellan

I used to live on the Cote d'Azur, which is what everyone else calls the French Riviera. The name comes from the blue color of the Mediterranean Sea, azur in French. In English, it is azure. But it is probably more well-known today as the name o...
- 10 Oct 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - Tensilica Neural Network Compiler: An Offline Tool for Efficient Deployment of Neural Networks

References4U

In this week’s Whiteboard Wednesdays video, Megha Daga describes how the Tensilica Neural Network Compiler works, from a trained floating-point network to an optimized source code generation for a Tensilica AI-enabled DSP or processor.

https://youtu.be/V9BV_BLIUiI
- 9 Oct 2018
System, PCB, & Package Design : How To Maintain Connectivity in a Multiboard PCB System

TeamAllegro
By John Burkhert Jr

Bringing a multiboard system together is a chance for the designer to spread their wings. As the circuit spreads, so do the risk of crossed signals. Some of the ways the circuits can get scrambled include:

Some connector vendors have clear indications of polarity. Others leave all numbering to the buyer. In the same way, a row of gold fingers will be anything we draw up in terms of pin numbers and…
- 9 Oct 2018
Breakfast Bytes: David White and Machine Learning

Paul McLellan

Recently Cadence held a worldwide event for our interns. To read more about our intern program, see my post CHIPs in the Cadence Cafeteria. The number varies almost on a day-to-day basis, but when I wrote that post we had 259 interns at 13 different ...
- 9 Oct 2018
Verification: Improving Your Testbench Flexibility with Enhanced Specman Templates

Steve Brown

Cadence® Specman® Elite delivers faster and higher quality verification at block, chip, and system levels. The tool is cloud ready, supports industry-standard verification languages, and is compatible with the Open Verification Methodology (OVM), the Universal Verification Methodology (UVM), and the eReuse Methodology (eRM), so you can quickly and easily integrate it with established verification flows. Attend…
- 8 Oct 2018
Verification: Specman 18.09: Avoiding the Small Annoying Mistakes

teamspecman

Specman 18.09: Avoiding the Small Annoying Mistakes

In almost every industry, one has the potential of making a small mistake that may cost hours or days to find. The following interesting article takes the small mistakes to the extreme and mentions a few cases of small mistakes that had a huge effect: Messing up big time: 10 tiny mistakes that have caused HUGE problems.

How is it relevant to Specman? As a verification…
- 8 Oct 2018
Verification: App Note Spotlight: Streamline Your SystemVerilog Code, Part IV - Dynamic Objects

XTeam

Welcome back to the fourth installment of a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked—Simulation Performance Coding Guidelines for SystemVerilog. This app note overviews all sorts of coding guidelines and helpful tips to help optimize your SystemVerilog code’s performance. These strategies aren’t specific to…
- 8 Oct 2018
Analog/Custom Design: Virtuoso: The Next Overture - Virtuoso RF Solution for High Frequency Product Designs

deeptig

The latest Advanced Methodology Virtuoso release (ICADVM18.1) introduces Virtuoso RF Solution that allows you to create modules and packages in Virtuoso by leveraging new package design capabilities.
- 8 Oct 2018
Breakfast Bytes: History of ISO 26262

Paul McLellan

I have known Kurt Shuler, the VP marketing at Arteris, for some time. But this post is not going to talk about NoCs (networks-on-chips) at all. It is about the history of ISO 26262. Kurt has been on the committee developing the standard for the secon...
- 8 Oct 2018
PCB、IC封装：设计与仿真分析: 基于团队协作的AC/DC电源完整性设计与分析方法

Sigrity

在与用户的交流中，我们收获了许多问题与建议：如何使用压降分析或AC分析技术、如何改进PCB设计流程、如何优化去耦电容的使用等等……这些问题推动着我们不断完善电源和信号完整性的设计。在这之中，有一个话题备受关注：我们的用户纷纷表示现有的在设计周期后期发现问题再反复与PCB或IC封装设计工程师多次沟通的方法是一大痛点。更糟糕的是，在某些情况下，该方法导致的设计周期的不可预测性严重损害了公司的利益。在PCB设计领域，人们日益认识到约束驱动的设计流程的重要性。该流程旨在设计...
- 5 Oct 2018
Breakfast Bytes: TSMC OIP Ecosystem Forum

Paul McLellan

Last Wednesday was the TSMC OIP Ecosystem Forum. The first part of the day was hosted by Dave Keller, President of TSMC America. He pointed out that it was the 10th anniversary of OIP. It has been a great success ensuring that EDA and IP are ready fo...
- 5 Oct 2018
Breakfast Bytes: EXTRA: Did the Chinese Really Attach Rogue Chips to Apple and Amazon's Motherboards?

Paul McLellan

Today, Bloomberg's BusinessWeek (BW from now on) published a story The Big Hack: How China Used a Tiny Chip to Infiltrate US Companies. The big question is whether they actually did or not. If they did, then this is the most brazen security breach th...
- 4 Oct 2018
Breakfast Bytes: PCB West: History of PCB

Paul McLellan

At PCB West recently, Wally Rhines gave one of the keynotes. It was titled Is Past Prologue? The Future of the PCB Design Industry. Wally said that it wasn't really his title, it was given to him by the show organizers who wanted him to do a retrospe...
- 4 Oct 2018
Breakfast Bytes: What's For Breakfast? Video Preview October 8th to 12th 2018

Paul McLellan

https://youtu.be/0CNhCWOxPKY Coming from TSMC OIP Ecosystem Forum, Santa Clara (camera Seena Shankar) Monday: The History of ISO 26262 Tuesday: ESD Alliance Digital Marketing Workshop Wednesday: Embargoed Announcement Thursda...
- 3 Oct 2018
Breakfast Bytes: Breakfast Buffet for September 2018

Paul McLellan

https://youtu.be/aWnEDVUQwoY The three highlighted posts for August were: The New Tensilica DNA 100 Deep Neural-network Accelerator CDNLive India Ambit Design Systems Sign up for Sunday Brunch, the weekly Breakfast Bytes email.
- 3 Oct 2018
System, PCB, & Package Design : The Day a PCB Was Born

TeamAllegro

By John Burkhert Jr

I want to take you back to a project that highlights a few twists as all good projects will. 17 years ago I was presented with 20 pounds of potatoes and a 10 pound bag. The bag was shaped like a PEZ dispenser with a crown of gold fingers in place of the plastic head. The actual name of the early form factor was XENPAK. It used the XAUI protocol which has become a popular 10G-for-the-masses deal. My…
- 3 Oct 2018
Breakfast Bytes: TSMC OIP Virtual Design Environment

Paul McLellan

Today, it is TSMC's 2018 Open Innovation Platform (OIP) Ecosystem Forum in the Santa Clara Convention Center. TSMC has two big events each year (in the US, they also take them on the road to other countries) and almost every major announcement ge...
- 3 Oct 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - Significance of Sparsity in Neural Networks

References4U

In this week’s Whiteboard Wednesdays video, Megha Daga discusses how handling sparsity positively affects bandwidth, performance, and power efficiency.

https://youtu.be/pgouTDPhjlQ
- 2 Oct 2018
Breakfast Bytes: EDPS: Experience Teaching Undergraduates EDA

Paul McLellan

At the recent EDPS, Cadence's Patrick Groeneveld presented about a course that he and other EDA luminaries taught at Stanford last year. I say "Cadence's Patrick" since he currently works here, but he worked for me at Compass Design...
- 2 Oct 2018
Breakfast Bytes: GlobalFoundries Executive Team Explains the Pivot

Paul McLellan

At the recent GlobalFoundries Technology Conference GTC there was a press and analyst lunch. Tom Caulfield (CEO), Gary Patton (CTO), and Bami Bastani (SVP of the business units) answered questions, Tom opened the proceedings by giving a little more d...
- 1 Oct 2018
PCB、IC封装：设计与仿真分析: 升级到Allegro17.2-2016的10大理由之6：平滑的弧形走线节省了柔板设计的走线设计时间

TeamAllegro

平滑的弧形走线是Cadence®Allegro®PCB Designer 17.2-2016的新功能，通过更有效的方法为用户提升设计效率。这一新功能在弧形走线的基础之上又得到了很大的提升，减少了对话框，引入了一个简单的基于图形界面的双状态点击使用模型，也可以推挤现有的连接线（即使是弧形走线也可以实现推挤）。非轮廓和轮廓走线之间的转换也很平滑。（点击查看大图）增强的弧形走线在Route > Unsupported Prototypes > Enable Enha...
- 28 Sep 2018

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