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Breakfast Bytes: Imec on EUV. Are We There Yet?

Paul McLellan

I already gave an introduction to my first visit to imec in my life in my post If It's Tuesday This Must Be Belgium. My First Visit to imec One of the things I mentioned there is that they have an EUV stepper in their fab, and they work clos...
- 12 Jun 2018
Breakfast Bytes: What's For Breakfast? Video Preview June 18th to 22nd 2018

Paul McLellan

https://youtu.be/puYFl7m50tM Coming from Dilijian Armenia (camera Gary Bengier) Monday: Why Millennial Engineers Should Work for Cadence Tuesday: Wrapup from the RSA Security Conference Wednesday: Dolby DAP Light Thursday: Automotiv Elektronik ...
- 12 Jun 2018
Verification: DMS 2.0 - What's Cool and What's New

XTeam

Are you aware of all the cool new features in Digital Mixed Signal 2.0 (DMS 2.0)? Provided with the Xcelium Parallel Simulator versions 17.10 and beyond, DMS 2.0 brings you all kinds of new and wonderful features to help you use Xcelium to verify your mixed-signal designs.

The level of interaction between analog structures and digital logic is a lot more complex than it used to be. Divide-and-conquer verification isn…
- 11 Jun 2018
Breakfast Bytes: FD-SOI vs FinFET: Dan Hutcheson Re-Runs His Survey

Paul McLellan

Recently, the SOI Consortium held its annual Silicon Valley Symposium. I was only able to attend in the afternoon since I spend the morning at the ESD Alliance workshop on digital marketing (for more on that, see my post Digital Marketing—With ...
- 11 Jun 2018
Analog/Custom Design: Virtuosity: Let's Have Fun with ADE Debugging – Part 1

Kabir

Over the years, we have seen our customers’ usage of ICRPs increase dramatically. It is now quite common to run 1000s of simulation points using 100s of ICRPs. And as this usage has increased, one of the challenges that has emerged is how to debug issues with ICRPs and job distribution, which is the topic of my write-up. So, what is it that I’m trying to address? Does the following sound familiar? User hits green button…
- 11 Jun 2018
Breakfast Bytes: Why Did EDA Have a Hardware Business Model?

Paul McLellan

Business models are really important. Just ask any internet startup company that has lots of users and is trying to work out how to monetize them. It is a lot easier to get people to use something for free, much harder to get people to pay for s...
- 8 Jun 2018
Analog/Custom Design: Virtuoso IC6.1.7 ISR20 and ICADV12.3 ISR20 Now Available

Virtuoso Release Team

The IC6.1.7 ISR20 and ICADV12.3 ISR20 production releases are now available for download. To find out more, click here…
- 8 Jun 2018
Verification: Speedup SystemVerilog UVM Debug Regression Time with Dynamic Test Load

XTeam

Microsemi has been evaluating a unique feature in Xcelium System Verilog UVM Dynamic Test Load for some time now, and they shared their thoughts on it in a paper presented at CDNLive San Jose April 2018.

One of the fields Microsemi operates in is the realm of optical networking. In optics, a given sensor’s input can vary wildly, but the way the input is processed is largely the same. Thus, a wide variety of tests are…
- 7 Jun 2018
Breakfast Bytes: Imec Roadmap

Paul McLellan

I recently visited imec. For an overview of my day, see my earlier post If It's Tuesday This Must Be Belgium. My First Visit to imec. One of the things that imec does is to take the funnel of potential process developments and get some ...
- 7 Jun 2018
The India Circuit: Indian Airports Go High Tech

Madhavi Rao

No more printed tickets. Shorter queues at check-in counters. Humanoid robots walking amidst you, giving you directions and guidance. Get ready for all this and more in just a few months from now. India is undergoing a technological revolution on ma...
- 6 Jun 2018
Verification: PCI-SIG Developer's Conference: What's New with Gen 5 and When Will it be Adopted?

Lana Chan

The release of PCIe 4.0 rev 1.0 in October 2017 was anticlimactic after the announcement of PCIe 5.0 rev 0.3 at last year’s PCI-SIG DevCon. Fast forward, this year’s DevCon has kicked off and the SIG is clearly demonstrating its commitmen...
- 6 Jun 2018
Breakfast Bytes: Heinz Nixdorf's Legacy in Paderborn

Paul McLellan

I read somewhere that the largest computer museum in the world is the Heinz Nixdorf MuseumsForum in Paderborn, which is in central Germany, a longish distance from anywhere I was likely to be. But after CDNLive EMEA, I visited imec in Belgium (s...
- 6 Jun 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - Verification Deliverables Required for Successful SoC Integration

References4U

In this week’s Whiteboard Wednesday, YJ Patil explains the importance of having a complete set of IP verification deliverables to speed SoC integration including: IP-XACT description, reusable testbench and test cases, system-level C tests, and user documentation.

https://youtu.be/Oc7BmOihvms
- 5 Jun 2018
Breakfast Bytes: What's For Breakfast? Video Preview June 11th to 15th 2018

Paul McLellan

https://youtu.be/IYm-CauwKTo Coming from Yerevan Armenia (camera Jack Darrow) Monday: Dan Hutcheson Reruns his FD-SOI vs FinFET Survey Tuesday: Imec on EUV. Are We There Yet? Wednesday: "I Couldn't Imagine Being Too Poor for ...
- 5 Jun 2018
Verification: RAK Attack: Verifying Power Intent for Low Power Mixed Signal SoCs

XTeam

The wait is finally over—the Rapid Adoption Kit (RAK) for verifying the power intent of low-power mixed signal SoCs is here! The RAK is a tutorial designed to clearly show, through example, how to verify one of the most critical technology convergences in IoT devices. It’ll talk about the differences in verification of a processor-based design whether it’s powered internally or externally, how to verify SPICE, SystemVerilog…
- 5 Jun 2018
Breakfast Bytes: A Computer Scientist Takes a Look at Mechanical Security

Paul McLellan

I wrote recently about visiting The Tech in San Jose. One of the exhibits showed you how a cylinder lock worked (and even how lock picks worked, since you could use them to open the lock without using a key). I mentioned an academic paper about maste...
- 5 Jun 2018
System, PCB, & Package Design : Designing a PCB in Harmony with Your 3D Extraction Expert

Sigrity

You know who we are talking about. The guy in the corner with all the PhDs hanging in his/her office. Everyone goes to Mr/Ms. 3D-Expert to get their 3D structures analyzed. He/She knows all the bells and whistles and can make a tool...
- 4 Jun 2018
Verification: App Note Spotlight: Streamline Your SystemVerilog Code, Part II - SystemVerilog Semantics

XTeam

Welcome back to a special multi-part edition of the App Note Spotlight, where we’ll continue highlighting an interesting app note that you may have overlooked—Simulation Performance Coding Guidelines for SystemVerilog. This app note overviews all sorts of coding guidelines and helpful tips to help optimize your SystemVerilog code’s performance. These strategies aren’t specific to just the Xcelium Parallel…
- 4 Jun 2018
Breakfast Bytes: TI Flies Pegasus in the Clouds

Paul McLellan

Kyle Peavy of Texas Instruments reported on their experience with Pegasus, Cadence's newish physical verification system, at CDNLive Silicon Valley. You won't be surprised to know that TI's chips are getting more complex and larger,...
- 4 Jun 2018
Breakfast Bytes: Samsung Foundry Forum: 10, 8, 7, EUV, 5, 4, GAA, 3...

Paul McLellan

Last week was the Samsung Foundry Forum. Almost exactly a year ago, Samsung reorganized so that foundry was a standalone business, a part of device solutions (along with memory, and system-LSI). As you might expect, US contributes the most revenue to...
- 1 Jun 2018
Verification: Empowering Generation - Range Generated Fields (RGF)

teamspecman

Specman constraints solver process consists of a series of reductions and assignments. It reduces the range of the field value based on the constraints, and then assigns to it a random value from the reduced range. After assigning one field, the range of all connected fields is reduced accordingly, and the process continues until all fields are assigned.

A new feature added in Specman 18.03 – Range Generated Fields…
- 31 May 2018
Analog/Custom Design: Virtuosity: How to Run a Multi-Technology Simulation (MTS)?

Priyanka Dadwal

Are you looking for some hands-on experience with running multi-technology simulation in Virtuoso ADE Explorer and Virtuoso ADE Assembler? In today’s fast-shrinking technology, we often have situations where we need to design custom IC system-in-packages (SiP). But, here comes the challenge – how to design these ICs using different technologies in a single design environment and analyze their responses when there are…
- 31 May 2018
Breakfast Bytes: It'll be HOT on Sunday Evening at DAC

Paul McLellan

For several DACs now, Heart of Technology (HOT) has run a party on Monday night. This year there is a HOT party...but it is on Sunday night after the DAC welcome reception. Heart of Technology is a philanthropic organization started by Jim Hogan...
- 31 May 2018
Breakfast Bytes: 7 Ways to Get the Most out of DAC

Paul McLellan

DAC, the Design Automation Conference, is coming up. It's Sunday June 24th to Thursday June 28th in San Francisco. But in a slightly new location: Moscone West. The other halls, Moscone North and South, are halfway through a major reconstruction,...
- 30 May 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - The Advantages and Trade-offs of HBM2 and GDDR6

References4U

In this week’s Whiteboard Wednesday, Marc Greenberg discusses the advantages and trade-offs of two advanced memory interfaces: HBM2 and GDDR6, both targeted to the high-performance computing market.

www.youtube.com/watch
- 29 May 2018

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