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Analog/Custom Design: Virtuosity: Automated Device Placement and Routing—WSP-Based Tree Style Device Routing

Sravasti

This blog provides an overview of the last step of the Virtuoso Automated Device Placement and Routing solution. In this blog, I'll talk about the key benefits of the Automated Device-Level Routing functionality.
- 27 Sep 2019
PCB、IC封装：设计与仿真分析: Ken的博客系列之八 | 千兆位串行链路接口的SI方法

Sigrity

作者：Ken Willis 上一篇：反向信道训练自动合规性检查有了详细的布局后互连以及IBIS-AMI模型的正确执行，您可以关注特定的、感兴趣的接口（本例中为PCI Express Gen 4）的合规性检查。每个接口都有自己的特定标准。在这种情况下，PCI Express确定了许多眼图相关的时域标准、无源互连通道的频域标准以及满足特定抖动容限范围的能力。单独评估这些标准可能会非常耗时，特别是，如果需要多次运行来扫描设计范围和多个通道模型的情形。用于通用串行链路标准的自动合规工具包通常会提...
- 27 Sep 2019
Breakfast Bytes: Building Neural Networks with High-Level Synthesis

Paul McLellan

Earlier this week, Dave Apte presented a webinar on AI Accelerator Design with Stratus High-Level Synthesis. It was timed for the East Coast and for Europe, so I had to get up at 6:00am to attend, but since I'm still somewhat jet-lagged from gett...
- 27 Sep 2019
Breakfast Bytes: TSMC OIP: 6nm and 5nm

Paul McLellan

Today it is TSMC's Open Innovation Platform Ecosystem Forum, or OIP for short. This is one of two events each year at which TSMC presents much of the status of their technology, their fab construction, and production schedules. The other is the T...
- 26 Sep 2019
Breakfast Bytes: Embedded Development: Specialized Processing

Paul McLellan

Yesterday, in Running the Program for an Embedded System, I wrote about using emulation and FPGA prototyping to test and debug the software load for an SoC. But I didn't discuss where the software came from, just that somehow there was some obje...
- 25 Sep 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - An Intuitive Introduction to Finite Element Analysis (FEA) for Electrical Engineers, Part 1

References4U

In this week's Whiteboard Wednesdays video, Tom Hackett begins a 2-part introduction to finite element analysis (FEA) by looking at a simple model of a bridge and showing why FEA techniques are required for analysis of real-world structures. For a detailed explanation of the mathematics behind Finite Element Analysis, see this excellent video by Grasp Engineering: Practical Introduction and Basics of Finite Element…
- 24 Sep 2019
Breakfast Bytes: Running the Software for an Embedded System

Paul McLellan

A big challenge with developing a modern SoC is developing the software. Not so much the development itself, which is not very different from any other software development, but running and debugging the software. Waiting for the silicon to...
- 24 Sep 2019
System, PCB, & Package Design : IC Packagers: Finding Design Issues in SiP - Three Options for DRC Management During Sign Off

Tyler

Your design is complete. Yet, you have 20 DRC violations that need to be addressed (whether that means correcting the constraint required value, modifying objects, or waiving the DRC to sign off on it as okay). What’s the best way to go about r...
- 24 Sep 2019
Analog/Custom Design: Virtuoso Meets Maxwell: Help With Electromagnetic Analysis—Part I

Kabir

This blog is the first one in the multi-part series that aims at providing some in-depth details of electromagnetic analysis in the Virtuoso RF solution. To learn about a few tips and tricks on the process setup, read
- 23 Sep 2019
Breakfast Bytes: CDNLive Israel 2019: Celsius, the Dead Sea, Ramallah

Paul McLellan

The big announcement at CDNLive Israel was during Anirudh's keynote when he announced the second product in the system analysis space, Celsius. This is a thermal solver using both finite element analysis (for the solid parts) and computation...
- 23 Sep 2019
Breakfast Bytes: Sunday Brunch Video for 22nd September 2019

Paul McLellan

https://youtu.be/6p94sN1fHFY Made at Tel Aviv seafront (camera Carey Guo) Monday: MLPerf: Benchmarking Machine Learning Tuesday: PCIe Gen 4: It's Official, We're Compliant Wednesday: Celsius: Thermal and Electrical Analysis Together...
- 21 Sep 2019
Breakfast Bytes: 500th Anniversary of Magellan's Voyage

Paul McLellan

Earlier this year, on July 20, we celebrated the 50th anniversary of the first landing on the moon. I wrote about it—well, mostly about the Apollo Guidance Computer—that day in my post The First Computer on the Moon. Increasingly, getting...
- 20 Sep 2019
Analog/Custom Design: Virtuosity: Automated Device Placement and Routing—Base Layer Fill Insertion

Sravasti

Welcome back to my next post in the Virtuoso Automated Device Placement and Routing blog series. At advanced node, after running the placer, there are a few additional requirements for base layers to be taken care of before the layout is routed and taken to completion. In this blog post, I’ll talk about how adding device fills helps meet these requirements. Read the post to know more.
- 19 Sep 2019
Academic Network: CDNLive Taiwan – Cadence User Conference 2019

Tracy Zhu

CDNLive Cadence User Conference is an opportunity for Cadence technology users, developers, industry experts, and academia to come together to network, share best practices on critical design and verification issues, and discover new t...
- 19 Sep 2019
The India Circuit: The Safety and Security of Autonomous Vehicle Systems

Madhavi Rao

At the recently-held CDNLive India 2019, Cadence’s annual user conference, we had a session by Cadence’s partners Green Hills Software. Green Hills Software is the worldwide leader in embedded safety and security. Cadence and Green Hills ...
- 19 Sep 2019
PCB、IC封装：设计与仿真分析: Ken的博客系列之七 | 千兆位串行链路接口的SI方法

Sigrity

作者：Ken Willis 上一篇：使用IBIS-AMI模型进行仿真反向信道训练均衡器自适应的另一项能力是反馈训练。许多高速串行协议规定SerDes接收器可以评估发射器送出的training patterns的信号质量，以此来决定发射器均衡的大小，然后将这个要求反馈给发射器，然后评估下一个training pattern。这个过程会重复多次，直到接收器对发射器的设置满意，那么这个满意的设置就会被实际传输出去。图1：反向信道训练（点击查看大图）尽管目前的IBIS标准还不支持反馈训练功能，...
- 19 Sep 2019
Breakfast Bytes: Programming Languages for Embedded Systems

Paul McLellan

How do you program an embedded system? Say, the code that runs on the control processor on a big SoC? What programming language should you use? I have never really programmed an embedded system, unless you count writing a couple of experimental progr...
- 19 Sep 2019
Academic Network: Xidian University: 2019 Student Summer Training Camp

Tracy Zhu

School of Microelectronics of Xidian University, was set up in 2004 which is one of the National Instruction Bases for Integrated Circuit Talents approved by the Ministry of Education of China, has been hosting a Student Summer Training Camp for 5 ye...
- 18 Sep 2019
Breakfast Bytes: Celsius: Thermal and Electrical Analysis Together at Last

Paul McLellan

Today at CDNLive Israel, Anirudh Devgan, Cadence's President, announced the Celsius Thermal Solver. This is Cadence's second product in the system analysis space, following on from the Clarity 3D Solver, announced at CDNLive Silicon Valley ea...
- 18 Sep 2019
Academic Network: Taiwan National IC Design Competition

Tracy Zhu

The Taiwan National IC Design Competition was a great opportunity for Cadence and the Academic Network to build our brand with students, connect with academia and attract top talent. This was the second year that we sponsored the ...
- 17 Sep 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Announcing Celsius Thermal Solver: A New Approach to System-Level Thermal Analysis

References4U

In this week's Whiteboard Wednesdays video, Be Gu introduces Celsius Thermal Solver, a new tool employing finite element analysis (FEA) techniques for thermal analysis of electronic systems. Ben explains how a novel architecture enables Celsius to deliver 10x capacity and performance improvements over existing solutions.

https://youtu.be/JrQbCZe9e8c
- 17 Sep 2019
System, PCB, & Package Design : BoardSurfers: PCB Electronics - Defining and Applying Physical and Spacing Constraints

mrigashira

If you get frequent calls from your fab houses or your customers regarding your product, or if your schematic, layout, and packaging engineers spend a lot of time exchanging notes about their requirements not being met, resulting in back and forth of designs, or if you believe, like most of us do, that a product should do what it was designed to do, constraints are your friends.
- 17 Sep 2019
Digital Design: Upcoming Webinar: AI Accelerator Design with Stratus HLS

dpursley

There is no doubt that 2019 has seen an explosion of artificial intelligence/machine learning usage for Stratus HLS. In fact, this momentum started in 2017.

Noting the increase in machine learning applications in our user base, we researched how to efficiently move from a TensorFlow model to hardware via Stratus HLS. By July 2018, AI startup Syntiant was talking at DAC about how they went from spec to tapeout in six …
- 17 Sep 2019
Breakfast Bytes: PCIe Gen 4: It's Official, We're Compliant

Paul McLellan

Way back in April 2016, I wrote a post about Cadence IP for PCI Express (PCIe) Gen4 where we demonstrated compliance with Mellanox (now part of NVIDIA). As Mellanox's Gilad Shainer said to me when I talked to him back then: interoperability...
- 17 Sep 2019
System, PCB, & Package Design : IC Packagers: Capture Your Design for Review

Tyler

How do you quickly show another developer an issue that concerns you? Do you need to send them the entire design, start a screen sharing session, or bring up the Symphony server and allow them to connect? All of these are GREAT review mechanisms; however, they aren’t always viable or convenient.
- 17 Sep 2019

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