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Analog/Custom Design: Virtuoso - The Next Overture: Introducing Simulation Driven Routing

Parula

The new release of the Virtuoso platform (ICADVM18.1) offers groundbreaking analysis capabilities and an innovational new simulation-driven interactive routing for more robust and efficient design implementation as well as extending our support for the most advanced users.
- 25 Sep 2018
Breakfast Bytes: CDNLive India: Invecas and FD-SOI

Paul McLellan

Today it is GTC, the GlobalFoundries Technology Conference. I will be there and I will cover what was said later in the week. When I was at CDNLive India a couple of weeks ago, one highly relevant presentation was by Invecas, titled PPA Strategies Us...
- 25 Sep 2018
Breakfast Bytes: EDPS: Design Process in Milpitas

Paul McLellan

For the second year, the Electronic Design Process Symposium (EDPS) took place in Milpitas, having been at Monterey for many years. This was apparently the 25th year EDPS has run. I find EDPS to be a fascinating conference, and I think it is a shame ...
- 24 Sep 2018
PCB、IC封装：设计与仿真分析: 升级到Allegro17.2-2016的10大理由之5：如何进行“叠层设计”？

TeamAllegro

在这我们谈论的不是您的叠层设计跟其他人比怎么样，而是您设计的PCB层叠结构，是刚性板、柔性板、刚柔板，或者使用了镶嵌技术。层叠的定义，更具体而准确的层叠的定义，是至关重要的。各种材料的安排会影响需要的阻抗控制和减少关键信号串扰的计算和分析，从而影响了最终产品性能。表达真实基材厚度（包括掩模层）的ECAD / MCAD协作对于系统物理建模至关重要，特别是对需要最有效利用空间的最小或最薄的设备。最重要的是，精确的层叠定义将被发送给电路板制造设备，来制造符合设计数据的最终产品。材料镶嵌（点击查看大...
- 21 Sep 2018
Breakfast Bytes: Jaswinder's Only Job Interview

Paul McLellan

On Labor day, I didn't get the day off since I was in Delhi. I had to labor, not celebrate it by eating barbecue. Instead, I ate chicken curry, naan, and fried okra at the lunch I had with Jaswinder Ahuja in a conference room. I knew he had ...
- 21 Sep 2018
Breakfast Bytes: What's For Breakfast? Video Preview September 24th to 28th 2018

Paul McLellan

https://youtu.be/NYsYkQzZADo Coming from SAP Center, San Jose (camera Sean) Monday: EDPS: Design Process in Milpitas Tuesday: CDNLive India: Invecas and FD-SOI Wednesday: RF Design with Cadence and National Instruments Thursday: G...
- 20 Sep 2018
Breakfast Bytes: Samsung Galaxy S9's Application Processor

Paul McLellan

At this year's HOT CHIPS, Jeff Rupley of Samsung presented the application processor that goes in their Galaxy S9 and S9+ smartphones. Apple only ever gives cursory information about their Ax chips, and I don't remember seeing a lot of detail...
- 20 Sep 2018
Breakfast Bytes: The New Tensilica DNA 100 Deep Neural-network Accelerator

Paul McLellan

Today, at the beautiful Tegernsee resort outside Munich in Germany, Cadence announced their latest processor IP, the Tensilica DNA 100 Deep Neural-network Accelerator. This is a highly scalable processor with a range from 0.5 TMACS (tera mu...
- 19 Sep 2018
Whiteboard Wednesdays: Whiteboard Wednesdays - Standalone AI Processor: Tensilica DNA 100 Processor IP for On-Device AI

References4U

In this week's Whiteboard Wednesdays episode, Megha Daga describes the new Tensilica DNA 100 Processor IP for on-device AI. This AI processor delivers industry leading high performance and power efficiency across a full range of compute from 0.5 to 100s of TMACs and is well suited for on-device neural network inference applications.

https://youtu.be/eT4f2CoBByo
- 19 Sep 2018
PCB、IC封装：设计与仿真分析: 为什么电源完整性(PI)是个“热”话题——如何进行电/热协同仿真

Sigrity

在设计新一代产品时，我们共同追求的目标都是“更快，更小，更便宜”。然而当这与更长的电池寿命和更低的功耗要求相遇时，就向我们提出了艰巨的设计挑战。唯一可以肯定的是，项目开发进度并不会因为我们需要克服挑战而延期。每个电子产品的设计师无疑都需要能够分析供电网络的工具。虽然元器件可以承受电源和地通路的某些波动，但这种容限是有限的。穿孔严重以至于像瑞士奶酪般的板层，以及为给信号布线腾出空间而在填充区域走线、打孔的做法只会加剧电压波动。但是当我们处于“更快，更小，更便...
- 18 Sep 2018
Breakfast Bytes: HOT CHIPS: Some HOT Deep Learning Processors

Paul McLellan

If there was a theme running through the recent HOT CHIPS conference in Cupertino then it was deep learning. There were two sessions on machine learning, but also every processor described in the server processor session had something to handle deep ...
- 18 Sep 2018
Breakfast Bytes: CDNLive India: Asynchronous Design

Paul McLellan

Every few years the idea of doing completely clockless design gets proposed again. This is also known as locally asynchronous design (no clocks at all), as opposed to simply having lots of clock domains and having asynchronous communication from one ...
- 17 Sep 2018
PCB、IC封装：设计与仿真分析: 三维建模与电磁场分析新工具——3D Workbench

Sigrity

在Cadence公司刚刚发布的Sigrity 2018版本中，介绍了全新的三维建模与电磁场仿真工具——3D Workbench。它具有当前市场上主流3D CAD 产品的用户界面（GUI），采用了经业界多年验证的PowerSI® 3D-EM仿真引擎（Engine）与多样且高效的网格划分（Mesh）选项。它的出现弥补了机械与电气仿真领域的隔阂。通过支持机械设计导入， 3D Workbench可在同一仿真模型中融合机械部件（如连接器、插座、接口等）与PCB、IC...
- 14 Sep 2018
Breakfast Bytes: Intel's Cascade Lake: Deep Learning, Spectre/Meltdown, Storage Class Memory

Paul McLellan

At the recent HOT CHIPS in Cupertino, Sujal Vora of Intel gave a look inside the Future Intel Xeon Scalable Processor (Codename: Cascade Lake-SP). To make sure we all stayed to the end, this was the last presentation in the conference. The three...
- 14 Sep 2018
定制IC芯片设计 : Virtuoso: 新序曲- Cadence Virtuoso “第18.1 交响乐” 的前奏曲

Rishu Misri Jaggi

Cadence Virtuoso is soon presenting a new symphony..."Symphony No. 18.1". Stay tuned in... Cadence Virtuoso “第18.1 交响乐”即将上线，敬请期待......
- 13 Sep 2018
Breakfast Bytes: Spectre/Meltdown & What It Means for Future Design 3

Paul McLellan

I gave an introduction to speculative execution and the vulnerabilities that have come to light this year in my post Spectre/Meltdown & What It Means for Future Design 1. Yesterday, I covered the first half of the keynote (John Hennessy, Paul Tur...
- 13 Sep 2018
Breakfast Bytes: What's For Breakfast? Video Preview September 17th to 21st 2018

Paul McLellan

https://youtu.be/3drxzhMFGD8 Coming from PCB West (camera Sean) Monday: HOT CHIPS: Some HOT Deep Learning Processors Tuesday: Intel Cascade Lake Wednesday: Embargoed Announcement from Tegensee Thursday: Samsung Galaxy S9...
- 12 Sep 2018
Verification: Come Join Us for "Deep Dive into the UVM Register Layer" - A Webinar From Duolos

XTeam
Join us on September 14th for a free one-hour webinar on the finer aspects of the UVM register layer. We’ll be focusing on key aspects of the UVM Register Layer that can help you with your UVM modeling in ways you may not be aware of.

We’ll be covering the following topics:

How to use user-defined front doors and back doors to expand what the register layer can do

Understanding the role played by the predictor…
- 12 Sep 2018
Analog/Custom Design: Virtuoso: The Next Overture - Congestion Analysis with a New Perspective

Parula

Watch out for the exclusive set of routing features, along with the newly introduced Design Planner features in ICADVM 18.1, and then take a fresh new look at the new Congestion Analysis assistant.
- 12 Sep 2018
Breakfast Bytes: Spectre/Meltdown & What It Means for Future Design 2

Paul McLellan

I gave an introduction to speculative execution and the vulnerabilities that have come to light this year in yesterday's post Spectre/Meltdown & What It Means for Future Design 1. There were 4 panelists at Hot Chips, chaired by Partha Rangana...
- 12 Sep 2018
Breakfast Bytes: Spectre/Meltdown & What It Means for Future Design 1

Paul McLellan

At HOT CHIPS, one of the "keynotes" was actually a panel of what I'll call industry luminaries. They were discussing the implications of vulnerabilities such as Spectre, Meltdown, and the recently announced Foreshadow. This is the most ...
- 11 Sep 2018
Breakfast Bytes: CDNLive India

Paul McLellan

CDNLive India took place last week. As usual, I made the long trip from California, nearly 30 hours door to door. There is aways something remarkable on these long flights and this time it was the WiFi pricing. It is nearly 50% more ($30.00 vs $21.99...
- 10 Sep 2018
System, PCB, & Package Design : New Sigrity 3D Workbench Used in Designing and Optimizing Next Generation High-Speed Connectors

Sigrity

2018 is going to be remembered as the year of 3D for Sigrity. As part of Cadence’s Sigrity 2018 release, we introduced the new Sigrity 3D Workbench technology included as part of the Sigrity PowerSI® 3D EM Extraction Option...
- 8 Sep 2018
PCB、IC封装：设计与仿真分析: 升级到Allegro17.2-2016的10大理由之4：行业领先的背钻能力

TeamAllegro

背钻的发展历程 15年来，在很多电子设计中处理5Gbps或更高频率的高速接口布线已越来越常见。在信号过孔上存在Stub的情况下，高速信号换层将会对信号完整性产生巨大影响。总的来说，这些短截线会造成阻抗不连续和信号反射，严重影响有效数据传输速率的提升。（点击查看大图）如何消除电子短截线？使用一种称之为背钻的制板工艺，有时也被称为控制深度过孔。做好规化和控制，保证高速信号走在特定的布线层，以此来减小Stub的影响。用盲埋孔和微孔技术来布高速信号，这种方案可以解决一些局限和担忧，...
- 8 Sep 2018
PCB、IC封装：设计与仿真分析: 升级到Allegro17.2-2016的10大理由之3：新的PAD编辑器——不只是一个新GUI

TeamAllegro

客户反馈是产品改善的关键当您在理解Allegro 17.2-2016发行版的特点和优势时，我可以猜到您在想什么。“哦不，他们对我的工作环境做了什么破坏？”如果您已使用Allegro多年了，您就会理解我的意思。我们称之为零版本的发行版被用来建立数据库/改变架构，会导致某种程度上的升级中断。17.2有效结合了零版本和17.0 EAP(Early Access Program)版本内容，于是就有了17.2。多年前，当我们在考虑下一步需要开发什么时，我们首先就要从你们提交的客...
- 8 Sep 2018

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