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If you missed joining or registering for the Boost Your Layout Productivity with Virtuoso Studio webinar, the complete recording is now available as a Training Byte at the Cadence support site.

This webinar will show you how to keep up with ever-changing layout requirements and challenges. We’ll also demonstrate Virtuoso Layout Suite capabilities that boost layout designer productivity in Virtuoso Studio, such as:…

3D heterogeneous integration (3DHI) technology creates high-performance systems by integrating different types of semiconductor chips or chiplets stacked vertically. Diverse functions such as processing, memory, and RF can thus be combined onto a single chip or package to improve performance and efficiency. As 3DHI systems increase in complexity, the importance of the Universal Chiplet Interconnect Express (UCIe) standard…

If you missed joining or registering for the Quantus Insight webinar, the complete recording is now available as a Training Byte at the Cadence ASK portal.

Running inside the Virtuoso Platform, the Quantus Insight Solution offers unique capabilities to analyse and mitigate layout parasitics in custom layout design. Particularly at advanced nodes, interconnect RCs can strongly affect design performance and power.

Engineered…

In the fast-paced world of analog and mixed-signal design, ensuring that your circuits meet stringent specifications is crucial. Enter Virtuoso ADE Verifier, a powerful tool designed to streamline and enhance the verification process for analog circuits. Whether you're an analog designer, verification lead, or project manager, Virtuoso ADE Verifier offers a comprehensive solution to meet your verification needs. It’s a…

On April 25, the UALink Consortium officially released the UALink 200G 1.0 Specification, marking an important milestone with support from key hyperscaler market players. It enables a low-latency, high-bandwidth fabric that supports hundreds of accelerators in a pod and facilitates simple load-and-store semantics.

The rapid evolution of Artificial Intelligence (AI) and Machine Learning (ML) is…

RAVEL, which stands for Relational Algebra Verification Expression Language, is designed for implementing system-in-package design rules. It builds on a relational view of the design data and is declarative in nature. RAVEL enables programmers to create new rules for the Allegro X PCB Editor and Allegro X Advanced Package Designer (APD) databases.

The updated online course for the RAVEL programming language introduces…

Semiconductors have revolutionized the world, powering everything from smartphones to space shuttles. But how did this incredible journey begin, and where is it headed? Welcome to Semiconductor 101 training, where we explore the fascinating evolution of semiconductor technology and its impact on our lives.

This course will introduce you to where semiconductors started and give you insights into where the semiconductor…

Modern microelectronics is a new operating theater for many in the Defense Industrial Base (DIB). It’s no longer a question of if but how to modernize. CadenceLIVE is replete with technical papers and keynote vision that form the field guide the DIB needs to move forward boldly.

While the full agenda has many worthy technical papers, I’ve used my experience as a principal investigator on multiple Defense programs…

Are you looking to level up your digital design skills—one byte at a time? Ohoo! I am supposed to ask this question at the end of this blog.

Ever feel like your brain is a sponge that’s just not soaking up enough? Or maybe you have tried to learn something new and ended up feeling like a cat chasing a laser pointer—excited but ultimately confused? Fear not, my friend! Microlearning is here to save the day, and it…

Today, let's break down time-of-flight (ToF) and how Tensilica Vision DSPs can be leveraged for depth sensing.

So, ToF? It's all about measuring depth. We've got two main types: Direct ToF (dToF) and Indirect ToF (iToF). dToF is like shouting and waiting for the echo—it measures the actual time it takes for light to bounce back.

Then there's iToF, where one figures out distance by comparing the phase…

In today's world of increasingly intelligent devices, efficient and reliable storage is paramount. Embedded MultiMediaCard (eMMC) has emerged as a crucial component that acts as the internal solid-state non-volatile storage for a wide range of devices handling on-device AI processing. Think of it as a compact, high-performing internal drive built directly into your phone, smart camera, or other embedded systems. This…

When you use Cadence’s Perspec System Verifier and the Portable Test and Stimulus Standard (PSS) to model your system, you will likely need a way to operate on the memory-mapped registers of various programmable devices within your system. This blog will guide you through the following processes:  

• Creating your PSS register model (or translating existing register metadata to PSS using Perspec’s pss_gen utility…