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Verification: How to Verify JEDEC DRAM Memory Controller, PHY, or Memory Device?

ssalehab

DDR Memory is an important part of a wide array of electronic system designs in various verticals like Data centers, Cloud computing, Aero-Defense, Mobile, or any other consumer devices. These industries continue to demand higher throughput, energy e...
- 29 Mar 2022
Analog/Custom Design: Virtuosity: Virtuoso-Innovus Interoperability — Making Trim Shapes Interoperable

Savita Thakur

Make your Virtuoso designs Innovus ready by ensuring trim and metal shapes follow the P&R routing style and are readable in Innovus.
- 29 Mar 2022
Life at Cadence: AI Unleashes Chip Designer Productivity

Kam Kittrell

EDA has a history of enabling breakthrough designer productivity. AI in EDA isn’t just making things better. Last year, we launched the biggest, baddest AI in EDA technology called the Cadence®︎ Cerebrus™︎ Intelligent Chip Explorer. It’s a revolutionary product that provides both optimized PPA and productivity benefits.
- 28 Mar 2022
Breakfast Bytes: Cadence: Sustainable by Design

Paul McLellan

Last week, Cadence published the Cadence Sustainability Report 2021 (link at the end of this post). As our CEO, Anirudh Devgan, says in the foreword: Our products enable the world’s leading electronics providers to optimize power, space, and e...
- 28 Mar 2022
Computational Fluid Dynamics: This Week in CFD #468

John Chawner

It's a sunny 81 degrees here in Fort Worth as I type this and after going outside for a few minutes after lunch I can tell you it's plenty warm. But not warm enough to melt a diamond which is the Image of the Week in our roundup of CFD news. What els...
- 25 Mar 2022
Verification: Who Inspires You? - An SVG Women's History Month Spotlight

Melisa

This month, we join millions celebrating and recognizing the achievements of women. We truly value the women who inspire us and have made a difference in our lives. In honor of Women's History Month, we asked our SVG community to share which wom...
- 25 Mar 2022
Breakfast Bytes: March 2022 Update: Intel Video, India, Apple

Paul McLellan

Amazingly, it is already the last Friday in March (and so the last Friday in Q1, it has flown by). So time for one of my update posts where I put stories that are too small to justify an entire blog post, and updates on topics I posted about earlier....
- 25 Mar 2022
Learning and Support: What is IEEE 1500 Wrapper Insertion Flow in Genus Synthesis Solution

MJ Cad

Are you searching for a scalable standard architecture for enabling test reuse and integration for embedded cores and associated circuitry? Are you looking for a standard that addresses testing strategies for the digital aspects of core designs withi...
- 25 Mar 2022
Digital Design: Mitigating Congestion, CTS, OCV and Other Challenges using Cadence Tools and Support

Vinod Khera

With the shrinking gemoetries and data-intensive endeavours of the upcoming industries like IoT, Robotics, Self-Driving Cars, 5G and 6G phones, designs are getting more complex. There are many challenges like congestion, routing, on-chip variations, and unconstrained paths that must be addressed. Cadence 24X7 support and rapid adoption kits (RAKs) helps customers by providing ready support and quick resolution.
- 25 Mar 2022
Breakfast Bytes: DVCon: UVM Birds of a Feather

Paul McLellan

At the recent DVCon 2022, there was a UVM Birds of a Feather meeting. UVM stands for the Universal Verification Methodology. The meeting was free to anyone at DVCon, even with just an exhibit pass. It was led by Mark Strickland who is chair...
- 24 Mar 2022
System, PCB, & Package Design : BoardSurfers: Specifying Layer Information for Multi-Layer Rigid and Flex Stackups

Sanjiv Bhatia

To manufacture a product that performs as you intended, it is imperative that you share accurate stackup definitions with the board fabricator or manufacturer. An accurate stackup definition is critical to getting the best possible performance from ...
- 24 Mar 2022
System, PCB, & Package Design : System Analysis Knowledge Bytes: The Road Ahead for Sigrity - An Interview with Brad Griffin

deeptik

In this blog, Brad Griffin (Product Management Group Director for Sigrity Marketing) talks about our product innovations, specifically Sigrity X, and shares his views about the future of system analysis.
- 24 Mar 2022
Breakfast Bytes: 3D Packaging Versus 3D Integration

Paul McLellan

A couple of weeks ago it was time for the 18th International Conference and Exhibition on Device Packaging (or IMAPS for short, although those are the initials of the organizer, the International Microelectronics Assembly and Packaging Society)....
- 23 Mar 2022
Computational Fluid Dynamics: Toyota Drastically Reduces Simulation Time with Automatic CFD Pre-Processing

AnneMarie CFD

Creating a detailed CFD model for automotive applications normally requires a huge amount of manual work. Toyota eliminates this work thanks to an innovative CFD pre-processing workflow, and in this on-demand webinar they will show you how. Watch how this allows them to quickly generate models, ready-to-run, with almost no human intervention, drastically reducing simulation turn-around time.
- 22 Mar 2022
Breakfast Bytes: DesignCon is Back In-Person and Cadence Will Be there

Paul McLellan

DesignCon is coming up April 5th to 7th. It takes place in the Santa Clara Convention Center. We will be there with a real booth, number 927. DesignCon is a somewhat confusing name for the conference. In the past, I've said it should be called the si...
- 22 Mar 2022
RF /マイクロ波設計: μWaveRiders:AWRソフトウェアを使用したRFカスケード性能の分析と最適化

RF Design Japan

RF設計者にとっての重要な課題は、ノイズと歪みの性能のためにRF系を最適化することです。 RF系のノイズと歪みを決定することは、カスケード分析として知られています。 Visual System Simulator（VSS）には、カスケード分析を支援する多くの測定があります。
- 21 Mar 2022
RF Engineering: μWaveRiders: Using AWR Software to Analyze and Optimize RF Cascade Performance

TeamAWR

A significant challenge for RF designers is the optimization of an RF chain for noise and distortion performance. Determining the noise and distortion as a progression through the RF chain is known as cascade analysis. Visual System Simulator (VSS) has many measurements that assist in cascade analysis.
- 21 Mar 2022
Analog/Custom Design: Virtuoso Meets Maxwell: Custom Passive Devices in RF Circuits - Devices or Interconnects?

Claudia Roesch

Virtuoso Electromagnetic Solver integration allows layered parasitic extraction and electromagnetic simulation with Cadence Quantus Extraction Solution and Cadence EMX Planar 3D Solver. The seamless integration automatically ensures that parasitic effects are neither missed nor double-counted during post-layout circuit simulation. But what am I doing with custom passive devices? How can I include the parasitics of the…
- 21 Mar 2022
Breakfast Bytes: Cadence Runs on AMD Processors, and AMD Uses Cadence to Design Those Processors

Paul McLellan

AMD EPYC 7003 designed with Cadence tools, and Cadence tools run on the new chip. With video.
- 21 Mar 2022
Breakfast Bytes: Sunday Brunch Video for 20th March 2022

Paul McLellan

https://youtu.be/C5tRh3gdAeo Made on my balcony (camera Carey) Monday: DVCon: PSS in the Real World Tuesday: Matter Wednesday: Industry 4.0 Thursday: Offtopic: Update Friday: Cadence recharge day Featured Post: 2021 Women in Technology Scholarsh...
- 20 Mar 2022
Life at Cadence: Celebrating Women around the World

Claire Ying

“Drive Your Own Development” Workshop in APAC The women in our Cadence SVG teams in Mainland China and Taiwan were thrilled to participate in a full-day career development workshop titled “Drive Your Own Development,” at the...
- 17 Mar 2022
Breakfast Bytes: Offtopic: Update

Paul McLellan

If you read Breakfast Bytes regularly, you will have noticed that I do a monthly "update" post, usually on the last Friday of the month, grouping together updates to existing posts and stories that are too small to justify writing a full bl...
- 17 Mar 2022
Verification: Addressing Hyperscalers' Requirements with Ethernet 800G

Krunal Patel

Cloud computing, IoT (Internet of Things), machine learning, big data, and data centers are a few of those buzzwords levitating around digital transformation in recent years and we are quite familiar with these terms. These technologies have much of a demand for things like excessive speed, higher bandwidth, scalability, and accelerated processing power.

Hyperscale computing provides an intelligible method of processing…
- 17 Mar 2022
Breakfast Bytes: Industry 4.0

Paul McLellan

Today we are at the dawn of the fourth industrial revolution, or Industry 4.0 as it is sometimes called. Let's start by looking back to the first three. It is well known that Henry Ford created the original assembly line. However, in some ways, i...
- 16 Mar 2022
Computational Fluid Dynamics: Meet Our Experts At The Seawork Commercial Marine Conference

AnneMarie CFD

Explore the challenges, changes and emerging opportunities in today’s and tomorrow’s commercial marine and workboat sector at Seawork in Southampton, UK - in person or online. Cadence will be there and is looking forward to meeting you. To learn more about Computational Fluid Dynamics software that functions as a virtual towing tank, make sure to pass by our booth or schedule a meeting with one of our experts (link provided…
- 16 Mar 2022

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