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RF Engineering: μWaveRiders: Cadence AWR Design Environment Customization

TeamAWR

The third in the series of AWR Design Environment Tips and Tricks, this blog highlights customization of the AWR Design Environment workspace to speed design creation and optimize use of AWR software.
- 15 Dec 2021
Analog/Custom Design: Virtuosity: Custom IC Design Flow/Methodology – Introduction

Ashish Patni

Read this blog for an introduction to the Custom IC Design methodology and the key design challenges that the methodology can help you address.
- 15 Dec 2021
Breakfast Bytes: The Old Order Changeth: Anirudh Becomes Cadence's CEO Today

Paul McLellan

Today, Cadence has a new CEO as Anirudh Devgan takes the baton from Lip-Bu Tan. In some ways, this is a big change. Anirudh becomes CEO today, and Lip-Bu transitions to being executive chairman of the board. In other ways, it is not as big an event ...
- 15 Dec 2021
Analog/Custom Design: Virtuoso ICADVM20.1 ISR22 and IC6.1.8 ISR22 Now Available

Virtuoso Release Team

The ICADVM20.1 ISR22 and IC6.1.8 ISR22 production releases are now available for download.
- 14 Dec 2021
Breakfast Bytes: The Outlook for Semiconductors...Especially in Cars

Paul McLellan

At the recent SEMICON West event, there was a media luncheon, which sounds rather grander than box lunches with sandwiches. Ajit Manoja, SEMI's CEO and president, kicked off the proceeding with a preview of what was coming in yesterday's press releas...
- 14 Dec 2021
Life at Cadence: My Life at Cadence: Evgeny Vlasov

Lautanen

We embrace a high-performance culture that is a core element of our “One Cadence - One Team” spirit. Our employees are committed to making a difference, and we support each other to think big, take risks, and shape the future of technolog...
- 14 Dec 2021
Breakfast Bytes: Costello's DAC Keynote

Paul McLellan

On the Wednesday of DAC, Joe Costello was back giving a keynote. The last time was in 2017 when he was CEO of Enlighted (since acquired by Siemens). Joe said it was the first time he'd given any sort of speech since the start of Covid. But before...
- 13 Dec 2021
Computational Fluid Dynamics: This Week in CFD

John Chawner

Another week of CFD behind us, another weekend of experimental fluid dynamics ahead of us, and the start of 2022 not too far away. What's does this week's CFD news include? Mathematicians have derived a mathematical formula with a compl...
- 10 Dec 2021
Breakfast Bytes: Thermal in Data Centers

Paul McLellan

You've probably heard that datacenters worldwide consume a huge amount of energy, and they do. The numbers vary depending on the source (and the data center) but a round number is that a data center consumes 100 MW. This number comes from the Ene...
- 10 Dec 2021
Verification: 5G Network Revolution for Enhanced User Experience and Industry Digitalization

Krunal Patel

The emerging 5G network is the 5th generation of the cellular network. A 5G network allows handling a thousand times more traffic than today's networks. Not only is it faster than the 4G network, but it also has lower latency, faster connectivity, and greater bandwidth. 5G network revolutionizes autonomous driving, the internet of things (IoT), virtual reality (VR), and user experience in the entertainment industry through faster download…
- 10 Dec 2021
CFD（数値流体力学): Omnis 5.2 国内公式リリース

CFD Japan

ケイデンスのCFD環境であるOmnisの最新版がリリースされました。プロジェクトやファイル管理の改良、ジオメトリ修正ツールの追加、マルチブロック構造格子、TurboおよびOpenソルバーの高速化など、様々な機能が追加されています。今回のアップデートでは、要望の多かった3つの改良点に着目しました。スライディングメッシュを使用した水車の非定常解析エンジニアや設計者は、水車やその他のターボ機械の非定常解析を行うことができるようになります。Omnis/Autogridでは、設定を維持したまま流路の...
- 9 Dec 2021
The India Circuit: Mentor Story: Prashant Vardhan Agarwal - Cadence Scholarship Program

Asim Khan

The Cadence Scholarship Program is the flagship CSR program of Cadence India, introduced five years ago. Many meritorious students from under-served sections of society drop out of the education system after school because of the lack of finances. Th...
- 9 Dec 2021
Computational Fluid Dynamics: Cadence is Funding Research on Adaptive Meshes for High-Speed Flows

John Chawner

This past summer, Cadence began funding research at the Massachusetts Institute of Technology (MIT) and the University of Tennessee at Knoxville (UTK) on a topic of significant current interest to the aerospace CFD community: mesh adaptation for high...
- 9 Dec 2021
Breakfast Bytes: Always-On Devices

Paul McLellan

One problem with battery-powered devices is that we increasingly expect them to interact with us without us pressing physical buttons. Our phone knows it is in our pocket. We can wake it up with a wake-word. Smart doorbells need to decide if there is...
- 9 Dec 2021
Digital Design: Voltus Voice: ESD Analysis Task Assistant: Your Key to 'Getting Started'

Anshika Gahlaut

This blog discusses the implementation of task assistant for the Voltus ESD analysis flow. ESD task assistant is an in-tool help access medium that facilitates the quick resolution of your ESD questions.
- 9 Dec 2021
Analog/Custom Design: Virtuosity: Tagging Variables and Corners in Virtuoso ADE Assembler

shubhangi upadhyay

You can now assign tags to variables and corners in Virtuoso ADE Assembler. Check out this blog to find out.
- 9 Dec 2021
Computational Fluid Dynamics: Webinar: Simulation of Hydraulic Turbines with Omnis CFD Platform

John Chawner

Join CadenceTECHTALK on December 15! Improving the design of modern turbomachinery requires highly accurate numerical simulations as they contain complex flow features that affect the performance of the machine. One such phenomena is the vortex rope...
- 8 Dec 2021
Computational Fluid Dynamics: More Control and Better Meshes in Pointwise Version 18.5

John Chawner

Automation in CFD mesh generation is of limited use if the resulting mesh isn’t suitable for the intended simulation. One of the many aspects of suitability is mesh quality, the distortion and skewness of the mesh elements relative to a perfect...
- 8 Dec 2021
Breakfast Bytes: The Cadence DAC Theatre...in Your Living Room

Paul McLellan

Historically at DAC, a large part of the booth was taken up by the Cadence Theatre where customers (and some Cadence people) would present their experiences in different market segments and with different tools. We decided this year to do it on video...
- 8 Dec 2021
Life at Cadence: My Life at Cadence: Sebastien Caussette

Lautanen

At Cadence, our strength as a company comes from our innovative ideas, collaborative spirit, and, most importantly, our connections with one another. Although many of us are working remotely, we have continued to find new ways to work together and dr...
- 8 Dec 2021
The India Circuit: Join Cadence at DVCon India 2021 Next Week!

Madhavi Rao

It's almost time for the event that Design and Verification engineers have been waiting for - DVCon India. Now in the 6th year, the Design and Verification Conference, or DVCon, is one of the premier industry conferences that can't be missed....
- 7 Dec 2021
System, PCB, & Package Design : (P)SpiceITUp: Using Curve-Fitting to Optimize a Design

mrigashira

If you are interested in the performance of a circuit that can be best described by a waveform instead of a value, say a practical filter circuit response, curve-fitting is the choice. You can use an external specification composed of measurement data defined in an external data file ...
- 7 Dec 2021
Breakfast Bytes: Cadence Endowments in Academia

Paul McLellan

Cadence has a long history of involvement with academia, going all the way back to the founding of SDA and the involvement of Alberto. In EDA, he's like Madonna and only needs a first name, partially because his real name is so long and his title...
- 7 Dec 2021
PCB設計／ICパッケージ設計: ASCENT: 17.4-2019 Hotfix 019以上に移行すべき更なる理由とは

SPB Japan

前回のブログに続き、Hotfix 019で新たに追加された興味深い変更点を見てみましょう。Allegro® System Captureは、一人で作業する設計者でも、小規模なチームに属する設計者でも、あるいは企業の大規模なチーム、分散したチームで仕事をしている設計者でも、誰でも利用することができます。回路設計機能のほとんどの部分は設計者にとって同じように機能しますが、一部の拡張機能は大規模な体制で利用される場合に有効に機能します。たとえば、一般的に、小規模な組織で作業する設計者はライブラ...
- 6 Dec 2021
Verification: From AMBA ACE to CHI, Why Move for Coherency?

MinL

Introduced back in 2011, ACE (AXI Coherency Extensions) grew from existing AXI protocol, to satisfy the cache coherency maintenance demands of SOCs with multi core processors and shared caches in smart phones, mobile computers, and servers. It added new channels for cache communication, extra signals to allow new transaction for coherency support, and five state model for caches.

AXI + ACE Signals:

ACE was designed…
- 6 Dec 2021

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