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Latest Blog Posts

  • Breakfast Bytes: How Intel Manufactures Chips

    Paul McLellan
    Paul McLellan
    I happened to be looking for something on YouTube recently when I came across this video on Intel's YouTube channel. It's a bit cutesy at the beginning ("Hi, I'm Chip"), but in five minutes it gives a pretty good idea of how ch...
    • 18 Mar 2020
  • 定制IC芯片设计 : Virtuosity:回顾定制IC芯片设计博客的黄金时代

    Dishika Majumdar
    Dishika Majumdar
    如果您错过了2019 发布的Virtuosity, Virtuoso Meets Maxwell 和Virtuoso Video Diary等博客专栏,或者您想了解已发布ISR中的增强功能,那么不要犹豫,请将此页面添加为书签,以获取相关信息。 另外,更多新的内容,请随时关注后续博客!
    • 17 Mar 2020
  • Analog/Custom Design: Virtuosity: Device Arrays in the Automated Device Placement and Routing Flow

    Sravasti
    Sravasti
    Since the release of the Automated Device Placement and Routing solution last year, we have continued to improve and build upon it. In this blog, I’ll talk about the latest addition—the Auto Device Array form—how this is an integral piece of the new Automated Device Placement and Routing solution.
    • 17 Mar 2020
  • System, PCB, & Package Design : New 3D Analysis Engine Offers Faster, More Accurate Simulations at Lower Cost

    Sigrity
    Sigrity
    A multi-CPU architecture running on both cloud and on-premise computers can better optimize large 3D structures in ICs, packages, and PCBs serving high-speed signaling designs.
    • 17 Mar 2020
  • Breakfast Bytes: Digital Full Flow for 5/7nm

    Paul McLellan
    Paul McLellan
    One constant in the semiconductor and EDA industries is, of course, Moore's Law. Another is the continual need for improved accuracy and performance. Accuracy is needed to take account of the effects that we used to be able to ignore. Performan...
    • 17 Mar 2020
  • Analog/Custom Design: Virtuoso Meets Maxwell: Bumps, Bumps.... Where Are My Bumps?

    Brian LaBorde
    Brian LaBorde
    Bumps are central to the Virtuoso MultiTech Framework solution. Bumps provide a connection between stacked ICs, interposers, packages, and boards. Bump locations, connectivity, and other attributes are the basis for creating TILPs, which we combine to create system-level layouts.
    • 16 Mar 2020
  • Breakfast Bytes: Another Year of CadenceLIVE—with Updated Schedule

    Paul McLellan
    Paul McLellan
    It's not strictly true that it is another year of CadenceLIVE since we called the event CDNLive in the past. But it's time for my annual preview of the season of CadenceLIVE events around the world. It is primarily a conference for users of Cadence ...
    • 16 Mar 2020
  • Verification: RAK Attack: Better Driver Tracing, Faster Palladium Build Time, UVM Register Map Automation

    XTeam
    XTeam

    Looking to learn? There's a bunch of new RAKs (Rapid Adoption Kits) available online now!

    1) Indago 19.09 Better Driver Tracing and More

    Are you new to Indago and not sure where to start? Luckily, there’s a new Rapid Adoption Kit for you: the Indago 19.09 Overview RAK! This neat package contains everything you need to get your debugging started through Indago. In four short labs, plus a brief introductory lab, you…

    • 14 Mar 2020
  • Breakfast Bytes: Another Year, Another Book of Breakfast Bytes

    Paul McLellan
    Paul McLellan
    There is a new edition of A Year of Breakfasts. How do you get a copy? You can get a free copy by attending any CadenceLIVE event this year. The picture below is a group of happy recipients of signed copies of last year's book when I was at CDN...
    • 13 Mar 2020
  • The India Circuit: Is Every Day Really Women's Day? Yes And No.

    Madhavi Rao
    Madhavi Rao
    This week had a plethora of posts and articles on International Women's Day (IWD) that is celebrated on Mar 8. In fact, there are two blogs on the Cadence community page – one by Paul McLellan, and the other by Ashley Sneathen about the Cad...
    • 12 Mar 2020
  • Breakfast Bytes: Breakfast Nibbles: Predictions for 2020...Plus How Did I Do in 2019?

    Paul McLellan
    Paul McLellan
    Last year in my post Breakfast Nibbles: Predictions for 2019, I made various predictions for the year. Let's see how well I did. The predictions were also republished as the last chapter of last year's A Year of Breakfasts. 2019 Predictions ...
    • 12 Mar 2020
  • System, PCB, & Package Design : BoardSurfers: Training Insights: Creating Custom Reports using ‘Extract’

    Shreyansh
    Shreyansh
    You must deal with many reports in your daily life – for your health, financial accounts, credit, your child’s academic records, and the count goes on. Ever noticed that these reports contain many details, most of which you don’t wa...
    • 11 Mar 2020
  • Breakfast Bytes: Exponential Growth

    Paul McLellan
    Paul McLellan
    In the semiconductor industry, we've been dealing with the exponential growth associated with Moore's Law for over 50 years. Even so, I don't think that gives us an intuitive understanding of exponential growth. Nobody seems to have a feeling about ...
    • 11 Mar 2020
  • System, PCB, & Package Design : IC Packagers: The Different Types of Mirrors

    Tyler
    Tyler
    I’m not talking about carnival funhouse mirrors, but rather the different options for mirroring symbols, vias, and bond fingers in your IC Package layout. The Allegro Package Designer Plus and SiP Layout tools have two distinct styles of m...
    • 10 Mar 2020
  • Breakfast Bytes: The Future's So Bright You've Gotta Wear Shades

    Paul McLellan
    Paul McLellan
    The Cadence website looks different, doesn't it? We are obviously in the middle of a re-branding. This re-branding is driven by two things. One is just that it is good to refresh the look of the company from time to time so that it doesn't get dated....
    • 10 Mar 2020
  • Analog/Custom Design: Virtuoso Meets Maxwell: Common Goal for One Flow, Acquisitions Strengthen RF Flow

    michaelthompson
    michaelthompson
    Seven months ago, I pointed out the ongoing need for change, or revolution, in high-frequency design flows. Spreading design IP across multiple, unconnected tools, is leading to manufacturing and design errors. It also slows the design flow and forces designers to focus on keeping track of edits and updates and not on innovating. Keeping track of the right s-parameter file may be a necessary evil in your current design…
    • 9 Mar 2020
  • Breakfast Bytes: International Women's Day and Mentoring Women at Cadence

    Paul McLellan
    Paul McLellan
    March 8 is International Women's Day, this year falling on a Sunday. When you read this, it will probably be Monday (or later). Normally I don't post on Sundays, but this time I'm making an exception to get the date right. You might assume that Inter...
    • 8 Mar 2020
  • Breakfast Bytes: Sunday Brunch Video for 8th March 2020

    Paul McLellan
    Paul McLellan
    https://youtu.be/oAtYdiwqPIw Made in front of my TV (camera Carey Guo) Monday: FCC Moves to Clear C-Band for 5G Tuesday: From Bootstrapped Startup to Profitability—with Lunch Wednesday: RSAC: Motherhood and Apple Pie...and Breaking into a Priso...
    • 8 Mar 2020
  • PCB、IC封装:设计与仿真分析: 极致PCB设计全流程 | 技巧一:如何设置参数定制最佳视窗

    SDA China
    SDA China
    设计图纸导入之后,我们即将启动PCB设计,如何使我们的设计过程能更加得心应手? 请紧跟我们的学习内容,本期将分享设计工具的参数设置,使我们更好掌控设计(演示工具为Allegro® PCB Designer软件): 根据设计需求,定制适用的最佳视窗及参数 根据连接关系不同,设置鼠线颜色 鼠标悬停时,显示强相关信息 关注微信公众号“Cadence楷登PCB及封装资源中心”,在微信后台回复关键词“PCB全流程”即可get完整课程计划与资料汇总...
    • 6 Mar 2020
  • Digital Design: Library Characterization Tidbits: Exploring Intuitive Means to Characterize Large Mixed-Signal Blocks

    AbhaRawat
    AbhaRawat
    Let’s review a key characteristic feature of Cadence Liberate AMS Mixed-Signal Characterization that offers to you ease of use along with many other benefits like automation of standard Liberty model creation and improvement of up to 20X throughput.
    • 6 Mar 2020
  • System, PCB, & Package Design : IC Packagers: Five Steps to IC-Driven Package Design

    mrigashira
    mrigashira
    They say Moore's law is slowing. It may be slowing but it is still running - it has not stopped! And, it has been running at full throttle for quite a few decades now.  The net result of this run? Well, you can't design ICs in isolation from the...
    • 5 Mar 2020
  • Analog/Custom Design: Virtuoso Video Diary: Knowledge Booster Training Bytes – Part 2

    Dishika Majumdar
    Dishika Majumdar
    Learn more about Cadence Education Services with this blog, which includes a list of training programs for various Virtuoso products and guidance on how to become Cadence certified in a certain technology or skill.
    • 5 Mar 2020
  • Breakfast Bytes: Razor Blades, Banking, and Antitrust

    Paul McLellan
    Paul McLellan
    One person whose opinions I value is Ben Thompson of Stratechery. He produces a daily newsletter from his lair in Taiwan but once a week it is free for anyone to read (I don't have a subscription so I only see the free ones). Also, roughly weekl...
    • 5 Mar 2020
  • System, PCB, & Package Design : BoardSurfers: Bending the Flex Boards

    mrigashira
    mrigashira
    When you design a rigid-flex board, the focus is, of course, on the bend. Your design might be bend to install (stable flexion) - it will be bent only a few times while installing. Or it might be dynamic - it will be bent regularly. It's important to...
    • 4 Mar 2020
  • Breakfast Bytes: RSAC: Motherhood and Apple Pie...and Breaking into a Prison

    Paul McLellan
    Paul McLellan
    There is always an interesting sounding presentation at RSA that looks like it might be a good blog post topic just based on the title. This year it was I Had My Mom Break Into A Prison Then We Had Pie by John Strand of Black Hills Information ...
    • 4 Mar 2020
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