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PCB、IC封装：设计与仿真分析: 2019七大行业动向预测

SDA China

本文翻译自Cadence “Breakfast Bytes”专栏作者Paul McLellan文章 “Breakfast Nibbles: Predictions for 2019"。新年伊始，我来和大家聊聊我眼中的2019年业内主题趋势。内存价格 2018年，整个半导体市场非常强劲，其中很大一部分原因是内存市场尤其是DRAM市场的需求远大于现有产能。而随着额外产能的上线，关注内存市场的人无一不认为其价格将会发生下滑（更多详细内容，请阅读 "Semicon...
- 3 Feb 2019
Breakfast Bytes: Sunday Brunch Video for 3rd February 2019

Paul McLellan

https://youtu.be/CXTltDRjb-M Made at DesignCon 2019 (camera Sean) Monday: IEDM: Embedded Memories Tuesday: CES: 5G, All Hat and No Cattle Wednesday: Persistent Memory Thursday: What Next for Modus DFT? Friday: Programming Persistent Memory www.b...
- 3 Feb 2019
Breakfast Bytes: Programming Persistent Memory

Paul McLellan

I talked earlier this week about the recent persistent memory summit (see my post Persistent Memory). If DRAM gets faster or higher capacity, then there isn't anything that software engineers need to change, whether they're writing the operating syst...
- 1 Feb 2019
Analog/Custom Design: Virtuosity: Simulation Planning and Coverage Environment (SPACE)- Introduction

Yagya Mishra

An important requirement for project sign-off is to ensure that all the design simulations in ADE Assembler are run using the efficient (or pre-defined) sets of operating conditions (corners, sweeps, model files and so) in accordance to the project. ADE Assembler and ADE Verifier now allow you to plan and create project-specific master setups that you can use to create setups for individual tests in ADE Assembler. This…
- 31 Jan 2019
Breakfast Bytes: Persistent Memory

Paul McLellan

Last week was the latest Persistent Memory Summit. In the semiconductor world, we don't usually use that word, we say non-volatile memory. In practice, this mostly means flash memory (mainly 3D NAND today) and embedded flash memory (eFlash). Both...
- 30 Jan 2019
Breakfast Bytes: What Next for Modus DFT?

Paul McLellan

I sometimes say that test is the red-headed stepchild of EDA, that doesn't get the same glory as the more high profile parts of the EDA flow such as synthesis, or place & route, or signoff. Test History Over the years, how we do test has...
- 30 Jan 2019
Verification: Specman is Sweet – Bosch Sensortec's Story

XTeam

Recently, Bosch Sensortec has been using Specman for their functional verification needs in their Inertial Measurement Unit, and they’re loving it.

Why is Specman so cool? Well, it’s implementing the familiar UVM in e, which provides the tools and infrastructure to easily build extendable, maintainable, and reusable verification components. If you use Specman, you’ll see big productivity increases. For a lot of…
- 29 Jan 2019
Breakfast Bytes: CES: 5G, All Hat and No Cattle

Paul McLellan

Increasingly, CES seems to be less about consumer electronics, and more about the big tectonic shifts in technology. Indeed, CES is no longer the Consumer Electronics Show, it is just CES. Of course, there were flexible screens (one you can even roll...
- 29 Jan 2019
Analog/Custom Design: Virtuosity: Introducing the Pin Tool

Priya Sriram

The Pin Tool follows an object-based approach to working with pins by consolidating and redefining the tasks under one umbrella. Various pin-related tasks are grouped in a logical design flow in the various menus in the Pin Tool. The tool includes several new options that let you perform a wide range of pin-related tasks.
- 28 Jan 2019
Life at Cadence: Empowered to Support Our Community

MeeraC

Cadence understands that the success of our business, our employees, and the community are fundamentally tied together. As part of creating a strong work environment and reinforcing our One Cadence—One Team values, we know it is important for o...
- 28 Jan 2019
Verification: New Training Bytes Available Now: All About SystemVerilog Classes

XTeam

If you’re leaving 2018 with the feeling that your SystemVerilog skills are lacking, don’t worry—there’s a new series of Cadence Training Bytes to help you hit the ground running in 2019. Here you’ll find eight new YouTube videos all about SystemVerilog classes.

You can find the first video here.

Here’s a quick table of contents:

SystemVerilog Classes 1: Basics

This video goes over the…
- 28 Jan 2019
Breakfast Bytes: IEDM: Embedded Memories

Paul McLellan

On the Sunday of IEDM are two short courses, one memory-focused, and one logic-focused. I always attend the logic one since that is more relevant to the broad semiconductor industry and to EDA in particular. But SoCs mostly (all?) have memories ...
- 28 Jan 2019
Breakfast Bytes: Sunday Brunch Video for 27th January 2019

Paul McLellan

https://youtu.be/1gxIy7TGg3c Made at EBC (camera Sean) Tuesday: DesignCon: The Integrity Show Wednesday: Why the Nation That Invented the Computer Lost Its Lead Thursday: "The First Half of 2019 Is Likely to Be Really Bad" Friday:...
- 27 Jan 2019
PCB、IC封装：设计与仿真分析: Cadence Sigrity 邀您莅临DesignCon 2019

Sigrity

时间：1月29-31日地点：Santa Clara Convention Center，美国加州 Cadence诚邀您莅临DesignCon #711 展台，了解如何利用Cadence® Sigrity 的信号完整性和电源完整性工具、多千兆SerDes分析、高级DDR IP和设计/分析工具、自动化IBIS-AMI模型创建、集成电子/光子设计自动化和为下一代2.5D和3D IC设计研发的高级IC封装和跨平台解决方案来攻克设计难题。并通过现场demo及会议研讨了解我们最新的软件技术和实用...
- 25 Jan 2019
Breakfast Bytes: Amazon Go: Just Walk Out Shopping

Paul McLellan

Last year you probably heard about Amazon Go when it opened in Seattle. This is a store where you install an App on your smartphone, go to the store, use a barcode the App shows to open the turnstile to get into the store, just take what you want off...
- 25 Jan 2019
Analog/Custom Design: Spectre Tech Tips: Optimizing Spectre APS Performance

Stefan Wuensche

This blog discusses how to optimize the Spectre APS performance for analog and mixed-signal designs. It introduces the key options for adjusting simulation accuracy and performance, provides solutions for typical setup problems causing performance issues, and delivers tips on advanced methods for optimizing simulation performance.
- 24 Jan 2019
Breakfast Bytes: "The First Half of 2019 Is Likely to Be Really Bad"

Paul McLellan

The title of this post was the single line summary of Dan Niles' quarterly outlook for the semiconductor industry. Dan is the founder and portfolio manager of AlphaOne NexGen Technology Fund. Each quarter GSA has a conference call with him where ...
- 24 Jan 2019
Breakfast Bytes: Why the Nation That Invented the Computer Lost Its Lead

Paul McLellan

Last month I wrote about a piece that Lynn Conway wrote for IEEE Computer Magazine. (See my post The Conway Disappearance Effect.) I came across another article in the same issue, When Winning Is Losing: Why the Nation that Invented the Computer Lost...
- 23 Jan 2019
Breakfast Bytes: DesignCon: The Integrity Show

Paul McLellan

It's the end of January and that means DesignCon. It is January 29th to 31st in the Santa Clara Convention Center. Increasingly, the design of high-end PCBs is all about integrity: signal integrity, power integrity, EM integrity, thermal integrity. F...
- 22 Jan 2019
The India Circuit: A Boost For Fabless Chip Design in India

Madhavi Rao

There was a lot of excitement when the National Policy on Electronics was announced in 2012. However, in the six years that it has been in existence, it has not proven to be very effective in its aim of stemming the outflow of foreign exchange for el...
- 21 Jan 2019
Breakfast Bytes: Sunday Brunch Video for 20th January 2019

Paul McLellan

https://youtu.be/Bs5A09med6Q Made at the Cadence campus in the rain (camera Sean) Monday: Tensilica at CES Tuesday: AMD Keynote at CES Wednesday: AlphaZero: Four Hours to World Class from a Standing Start Thursday: IEDM: EUV, the Road to HV...
- 20 Jan 2019
PCB、IC封装：设计与仿真分析: 了解DDR5技术之前需要知道什么是AMI与IBIS

Sigrity

本文翻译自Cadence "Breakfast Bytes"专栏作者Paul McLellan文章" AMI and IBIS: Who Put the Eye in AMI?"。 space 在SerDes设计领域，IBIS和AMI是对SerDes通道进行建模的方式，可以在保证设计性能的前提下，确保信号成功地在不同芯片之间进行传输。当下，我们的行业正面临着巨大的变化，IBIS和AMI的含义需要被更多设计领域的人了解。DFE均衡（判决反馈均衡）即将被规定包含在DDR5标准之内，这将需要运用IB...
- 18 Jan 2019
Breakfast Bytes: MLK Off-topic: The Lady with the Polar Chart

Paul McLellan

It's Martin Luther King day on Monday, and Cadence is off. I think that this is the first time I have ever got it as a holiday, rather than moving it to somewhere like July 3rd. Breakfast Bytes will not appear on Monday. So, as is traditional, th...
- 18 Jan 2019
System, PCB, & Package Design : Cadence Sigrity at DesignCon 2019

Sigrity

Happy new year! We want to invite you to visit us in booth 711 on the DesignCon Expo floor. Learn about how we can address your design challenges with Cadence® Sigrity signal integrity and power integrity tools, multi-gigabit SerDes...
- 17 Jan 2019
Analog/Custom Design: Virtuosity: What's New in Run Plan – Part III

Priyanka Dadwal

After two interesting blogs by Yagya Mishra that explained the most popular features of the Run Plan assistant in Virtuoso ADE Assembler , I am writing this third blog in the series to share with you the latest features introduced in the IC6.1.8 and ICADVM18.1 releases.
- 17 Jan 2019

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