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Analog/Custom Design: Virtuoso IC6.1.8 ISR2 and ICADVM18.1 ISR2 Now Available

Virtuoso Release Team

The IC6.1.8 ISR2 and ICADVM18.1 ISR2 production releases are now available for download.
- 19 Mar 2019
Breakfast Bytes: RSA: From Helen Mirren to Tina Fey

Paul McLellan

The RSA Security Conference that took place in the first week of March was bracketed by two women who don't have much connection to security. The main keynote session on Tuesday morning started with the lights going down, and then the announcer&#...
- 19 Mar 2019
System, PCB, & Package Design : BoardSurfers: Allegro 3D Canvas—Visualize the Board as You Design

Monika

Today’s dense and complex PCB designs require realistic 3D view to investigate the design issues way before they are ready for manufacturing. The complexity of the PCB designs is increasing significantly with time and visualizing all the design components to address electronic and mechanical design issues in a single consistent environment has become a challenge.

To cater to this need Cadence® Allegro® PCB Design…
- 18 Mar 2019
Analog/Custom Design: Virtuosity: Maestro Plotting Templates

Chandrika Durbha

Waveforms, plots, graphs, measurements, markers... are all a part and parcel of any circuit designer’s everyday life. For a regular user of Virtuoso ADE Explorer or Virtuoso ADE Assembler and the ADE waveform window, packaged with IC6.1.6/IC6.1.7 release, it was a common task to redo the measurements on plots every time the plot was refreshed or when a new simulation was set up. How about a feature that lets you save…
- 18 Mar 2019
Breakfast Bytes: The World Wide Web Was Born 30 Years Ago This Month

Paul McLellan

In March 1989 at CERN, a guy called Tim-Berners Lee had an idea about how to get control over the sprawling documentation mess at the organization. CERN is the European Particle Physics Laboratory. The name comes from French, Conseil Europ&eacut...
- 18 Mar 2019
Breakfast Bytes: Sunday Brunch Video for 17th March 2019

Paul McLellan

https://youtu.be/b5eJJcHiOoY Made at Cadence building 9 lobby (camera Sean) Monday: PSA: Americans Will Need Visas for Europe Tuesday: MWC: Voice Enhancement, GPS, Ultrasound, and More Wednesday: Domain-Specific Computing 1: The Dark Ages o...
- 17 Mar 2019
Breakfast Bytes: Domain-Specific Computing 3: Specialized Processors

Paul McLellan

The last two days' posts have looked at the development of general-purpose processors, and why we are now in the age of special-purpose processors, including one particular type, the GPU. Today, I take a look at some of the other aspect...
- 15 Mar 2019
Breakfast Bytes: Domain-Specific Computing 2: The End of the Dark Ages

Paul McLellan

Yesterday looked at how general-purpose computer architecture changed during the period when Moore's Law and Dennard scaling were both working well, and when computer architects were coming up with more and more innovative architectures to get ex...
- 14 Mar 2019
System, PCB, & Package Design : Teardrops and Tapers – Improving Manufacturability and Yield Automatically

Tyler

Teardrops (also called fillets) are the blending area of a cline entry into a pad, while tapers are the gradual transition from one line-width to another along a path. These two core concepts appear in nearly any PCB or IC package substrate today. They act to smoothen the intersection of the two objects, eliminating acute angle acid traps while also contributing to better signal integrity along the path.

However, any…
- 13 Mar 2019
Breakfast Bytes: Domain-Specific Computing 1: The Dark Ages of Computer Architecture

Paul McLellan

This is the era of domain-specific computing. Or, to use the words of Dave Patterson and John Hennessey from their Turing Award acceptance presentation, the "New Golden Age of Computer Architecture." Of course, to have a New Golde...
- 13 Mar 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Solving Scan Compression Congestion Issues with Modus 2D Elastic

References4U

In this week's Whiteboard Wednesdays video, Rohit Kapur, Distinguished Engineer at Cadence Design Systems, discusses the topic of scan compression and the layout problems created as compression ratios grow. The Modus DFT Software Solution targets this impact using its patented physically aware 2D Elastic Compression architecture, without any impact on fault coverage or chip size. For more information, read the datasheet…
- 12 Mar 2019
Breakfast Bytes: Breakfast Buffet for February 2019

Paul McLellan

https://youtu.be/pNgkoWQE9A4 The three highlighted posts for February were: Who Is Green Hills? Tensilica ConnX B20 for 5G, and Automotive Radar/Lidar Signal Integrity for 112G Sign up for Sunday Brunch, the weekly Breakfast Bytes email.
- 12 Mar 2019
Breakfast Bytes: MWC: Voice Enhancement, GPS, Ultrasound, and More

Paul McLellan

At the recent MWC Barcelona, the conference fka Mobile World Congress, Cadence had a booth, as usual. The focus of what we showed was using Tensilica for various applications relevant to customers who attend MWC. Nobody wanders into our booth looking...
- 12 Mar 2019
定制IC芯片设计 : Virtuosity: 着色数据是否与MPT流程兼容？

KomalJohar

毋庸置疑，兼容的设计能提高公司的业绩和生产效率。任何不兼容的设计都会增加产品的设计周期。为了便于高阶工艺节点设计中，工程师能创建与多重图形技术（MPT）相兼容的设计流程，我们在多重图形工具栏上，引入了兼容检查功能（Compliance Checker）的选项。在设计过程中, 您肯定遇到过这样的情况，版图设计的图形有颜色信息，但是根据MPT 流程设置，这些图形却不需要着色，通过兼容检查功能，便能把它们标记出来，这个功能还能标出有颜色偏移的图形实例，这些图形实例根据MPT 流程本不应该发生颜色...
- 11 Mar 2019
Verification: And the Winner of the 2019 DVCon U.S. Best Paper Award Is...

XTeam

Another successful DVCon U.S. 2019 has come and gone, but this year had a particularly interesting highlight. With nearly 900 attendees, a bigger program of tutorials, panels, papers, and posters, and a sold-out expo, the Best Paper award was even more prestigious than ever before. This year, the award was renamed to the Stuart Sutherland Best Paper Presentation. Stu was a leading Verliog and SystemVerilog expert, and…
- 11 Mar 2019
Breakfast Bytes: PSA: Americans Will Need Visas for Europe

Paul McLellan

From 2021, Americans will need a visa for Europe. You read it here first! That means you'll need a visa to visit NXP, Arm, Bosch, Nokia, BMW, Infineon, ST Microelectronics, and many more companies in our industry. When I lived in France, there was so...
- 11 Mar 2019
Analog/Custom Design: Virtuosity: Reading Vector Files in Virtuoso Visualization and Analysis

Arja H

Prior to IC6.1.8 and ICADVM18.1, to view digital and analog waveforms along with the applied stimuli, it was necessary to run the simulations using both digital and analog solvers. This could be a time-consuming process. However, now you can read in the digital stimuli files directly into Cadence Virtuoso Visualization and Analysis, the ADE waveform window. In addition, you can plot the analog waveforms using the stimuli…
- 8 Mar 2019
Breakfast Bytes: Gin and Tonic: The Drink of Barcelona

Paul McLellan

One thing that is a big deal in Barcelona is gin and tonic, or G&T as it is usually called in Britain. But unlike in Britain (and the US, for that matter), it is always served in a big goblet like that to the left. It is not just a few bars, and ...
- 8 Mar 2019
Breakfast Bytes: CDNLive: Travels with a Bear

Paul McLellan

It's nearly time for the season of CDNLive events, which starts as always in Silicon Valley, works its way East to Europe, before going across the Pacific Ocean to Asia and working its way West with Japan, Taiwan, China, India, and Israel. F...
- 7 Mar 2019
Analog/Custom Design: Virtuosity: Identifying Those Traces

AdityaMainkar

With the ever-increasing number of simulations required to be run these days, the sheer number of plots can be overwhelming and it can be difficult to figure out which Cadence Virtuoso ADE XL, Virtuoso ADE Assembler or Virtuoso ADE Explorer history, test or corner each plot belongs to. To help with this, from IC.6.1.8/ICADVM18.1 Virtuoso Visualization and Analysis we have made identifying and comparing traces across…
- 6 Mar 2019
Whiteboard Wednesdays: Whiteboard Wednesdays - Diagnostics – What Makes Modus Diagnostics an Industry Leading Tool

References4U

Cadence distinguished engineer Rohit Kapur introduces diagnostic capabilities in IC testing. Kapur explains the metrics used to evaluate diagnostics tools and discusses why the Cadence Modus DFT Software Solution is the industry-leading solution. For more information, please visit www.cadence.com/modus

https://youtu.be/Q-j1t64DwoU
- 5 Mar 2019
Breakfast Bytes: MWC Part Dos

Paul McLellan

Yesterday I wrote my first post about MWC19 Barcelona. Today is the continuation of that. Part 2, or dos in Catalan, the local language in Barcelona. It's dos in Spanish too, but numbers in Catalan are mostly different: un, dos, tres, quatre, cin...
- 5 Mar 2019
Breakfast Bytes: MWC Barcelona

Paul McLellan

Last week it was MWC Barcelona. As seems to be the fashion, like with CES, MWC just stands for itself, and is no longer Mobile World Congress. I predicted in my preview post MWC Barcelona: 5G in Catalonia that this year it would be all about 5G....
- 4 Mar 2019
Breakfast Bytes: Sunday Brunch Video for 4th March 2019

Paul McLellan

https://youtu.be/wjX4hOvb9-I Made at MWC19 Barcelona (camera JD Estella) Monday: OFC: The Optical Fiber Communication Conference Tuesday: Tensilica ConnX B20 for 5G, and Automotive Radar/Lidar Wednesday: DesignCon: 5G for V2X Communication ...
- 3 Mar 2019
PCB、IC封装：设计与仿真分析: Allegro PCB Editor: 进阶使用技巧

TeamAllegro

本文将和大家分享Allegro PCB Editor的进阶使用技巧，旨在利用快捷键操作而减少鼠标点击次数，同时包含了定制特定的应用环境，让工具发挥最大效率的方法和示例。希望对PCB设计工程师有所帮助，使设计更加得心应手的同时事半功倍地高效完成工作！命令1：funckey z "zoom center; pick -cursor" 目的：在中心区显示您所选中的内容操作方法：将光标移动到要作为中心位置的位置，然后单击z键 space 命令2：funckey " " "pop bbdrill -...
- 1 Mar 2019

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