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The India Circuit: 7 Trends We Saw In 2018

Madhavi Rao

I did at 2017 retrospective last year and looking back at 2018 there was a lot that happened that is worth recapping. So here is my 2018 retrospective. 1. The semiconductor industry did well in 2018 According to the Semiconductor Industry Association...
- 21 Dec 2018
Breakfast Bytes: Off Topic: Are You Smarter Than Google?

Paul McLellan

It's the day before Cadence is shut down for the holidays. Breakfast Bytes will resume normal service on January 2nd. So today is something off-topic. I thought I'd talk about two very contentious problems in mathematics, that manage to get P...
- 21 Dec 2018
Analog/Custom Design: Virtuoso IC6.1.7 ISR23 and ICADV12.3 ISR23 Now Available

Virtuoso Release Team
The IC6.1.7 ISR23 and ICADV12.3 ISR23 production releases are now available for download at Cadence Downloads.

IC6.1.7 ISR23

ICADV12.3 ISR23

For information on supported platforms, compatibility with other Cadence tools, and details of issues resolved in each release, see:

IC6.1.7 ISR23 README

ICADV12.3 ISR23 README

The links above are functional at the time of publishing. If you encounter any links that are now…
- 20 Dec 2018
Analog/Custom Design: Spectre Tech Tips: How to Perform EMIR Analysis in ADE Using Spectre APS?

Stefan Wuensche

This blog introduces you to the basic Spectre EMIR/Voltus-Fi XL flow for analyzing IR drop and EM currents in the Virtuoso ADE environment. The Spectre EMIR/Voltus-Fi XL flow provides many advanced features, such as static EMIR, Static Power Grid Solver (SPGS) point-to-point resistance checking, power gate handling, signal net IR drop, differential IR drop, what-if analysis, and self-heating analysis. In addition, Spectre…
- 20 Dec 2018
Verification: Verification Reflections on 2018

fschirrmeister

In my predictions for 2018 I had identified five key trends driving verification in 2018 – Security, Safety, Application Specificity, Processor Ecosystems and System Design Enablement, all centered around ecosystems. Looking back now as the yea...
- 20 Dec 2018
Breakfast Bytes: Top 10 Hotel Pet Peeves

Paul McLellan

When it comes to hotels, I have simple tastes. As long as the bed is comfortable, the room is clean, the shower works, and the WiFi connects then I'm happy. When I am paying myself, I never opt for top-of-the-line hotels with top-of-the-line pric...
- 20 Dec 2018
System, PCB, & Package Design : 10 Things You Might Have Missed in 2018

TeamAllegro

We’re sure it’s been a busy year for you. So busy that you might have missed the discussions about a number of new features Cadence introduced to help make PCB design easier for you. Let’s a take a look back at 10 of this year’s innovations.
- 19 Dec 2018
定制IC芯片设计 : Virtuoso: 新序曲-针对团队设计的新方法—Concurrent Layout工具

Sucharita

任何任务，被划分为不同的小任务，并分配给不同的人，这样是不是能加速完成该工作？如果我们告诉您新发布的ICADVM18.1 中Layout XL的新特征- Concurrent layout工具，能够实现单元视图下，多个工程师同时进行工作。您是不是迫不及待想要了解更多？敬请阅读……
- 19 Dec 2018
Breakfast Bytes: The Breakfast Bytes Guide to Flying

Paul McLellan

I fly a fair bit, a little over 100,000 miles a year in the last few years. There are many people in Cadence who fly a lot more than me, but I write a blog and they don't. So I thought I'd write down my advice on how to travel on long-ha...
- 19 Dec 2018
Life at Cadence: What Makes Cadence a Great Place to Work?

MeeraC

Cadence was recently named number 15 on the 2018 list of the World’s Best Multinational Workplaces, according to global research and consulting firm Great Place to Work® and Fortune Magazine. This is the fourth year in a row that Cadence wa...
- 18 Dec 2018
Breakfast Bytes: The Economist on Silicon Supremacy

Paul McLellan

A couple of weeks ago, the cover story of The Economist was Chip Wars: China, America and silicon supremacy. For the last few years it has been the biggest story in the semiconductor industry. You may already know the incredible fact that the value o...
- 18 Dec 2018
Analog/Custom Design: Virtuosity: Doing Placement in a Row-Based Environment

Priya Sriram

At advanced nodes, Virtuoso provides the capability of defining row templates and generating row regions in the layout design. You can then use the automatic and assisted placement options to place devices, Modgens, and standard cells in these rows.
- 17 Dec 2018
Analog/Custom Design: Virtuosity: What Did I Miss in Virtuoso Visualization and Analysis and ADE during the IC6.1.7/ICADV12.3 ISRs?

Arja H

Maybe you've been stuck on a project that used an older version of Virtuoso, maybe you've just subscribed to these blogs or maybe you're a new user to Virtuoso and perhaps you don't know about the new cool features that have been added over the course of the IC6.1.7/ICADV12.3 ISRs. We have packed a huge amount of enhancements in, the count is over 1600! I can't detail all of them here, but I'll outline the major enhancements…
- 17 Dec 2018
Breakfast Bytes: CES Preview

Paul McLellan

It's nearly January so it is nearly the Consumer Electronics Show in Las Vegas, which takes place the first full working week of the year, so this year it starts on the evening of 7th, with an opening keynote (this year from LG, taking over from ...
- 17 Dec 2018
Breakfast Bytes: Sunday Brunch Video for 16th December 2018

Paul McLellan

https://youtu.be/izP9iUskcXQ Made at the Cadence Marketing Holiday Party (camera Sean) Monday: RISC-V: Real Products in Volume Tuesday: IEDM: All About Interconnect Wednesday: The Conway Disappearance Effect Thursday: Automotive Summit: The Road...
- 16 Dec 2018
PCB、IC封装：设计与仿真分析: PCB设计团队如何在布线之前发现并解决信号完整性问题

Sigrity

PCB设计团队面临的一个主要挑战是如何确保设计的按时签发。由于信号完整性工程师通常只能在设计周期的后期发现问题并提出更改要求，设计师们于是不得不一遍又一遍地重复设计 - >布线 - >重新布线这一循环。当SI专家发现与基本反射相关的SI问题如不正确的布线拓扑结构、丢失的终止信号、过冲、回铃或延长的延迟建立时，设计师们的工作则必须重头再来。这一切都令人感到沮丧，特别是当SI专家知道这些基本问题其实可以更早地得到解决。在设计后期发现问题，意味着设计团队之前投入的布线精力都白费了，他们...
- 14 Dec 2018
Computational Fluid Dynamics: A2V: Modeling Aerodynamics Lift for Workboats and Commercial Passenger Vessels in FINE/Marine

AnneMarie CFD

Author: Lionel Huetz, CEO, Advanced Aerodynamic Vessels, France Advanced Aerodynamic Vessels (A2V) develops and commercializes a new generation of fast transportation vessels using aerodynamics to improve energy efficiency. Its revol...
- 14 Dec 2018
Breakfast Bytes: Automotive Sensors: Cameras, Lidar, Radar, Thermal

Paul McLellan

Yesterday I wrote a sort of overview of the Cadence Automotive Summit that took place in November, in the post Automotive Summit: The Road to an Autonomous Future. Today, the focus in on a key part of automating driving, namely sensors. One of the fi...
- 14 Dec 2018
Breakfast Bytes: Breakfast Buffet for November 2018

Paul McLellan

https://youtu.be/SxGTX1reCVw The three highlighted posts for November were: Diwali, the Hindu Festival of Lights...and Photonics, the Silicon Festival of Light Inside Google's TPU Mechanical, Thermal, EMI, SI, PI: PCB Design Needs Them All Sig...
- 13 Dec 2018
Digital Design: 2018 Annual HLS Survey Results

dpursley

Earlier this year, we performed the annual high-level synthesis (HLS) industry survey to get an idea of the industry’s expectations of HLS. As in last year’s survey, approximately half of the responses were from current HLS users, and half were from non-users. This year’s anonymous survey focused on HLS usage and expectations.

As usual, I’ll walk through the questions one by one below, but first let…
- 13 Dec 2018
Breakfast Bytes: Automotive Summit: The Road to an Autonomous Future

Paul McLellan

Before Thanksgiving, Cadence held an Automotive Summit. I was going to dive into some of the detailed material presented, but it occurred to me that it might be a good time to step back and take a look at where we are in the industry as a whole. I&#3...
- 13 Dec 2018
定制IC芯片设计 : Virtuoso: 新序曲—针对高频产品设计的Virtuoso RF解决方法

deeptig

最新发布的Advanced Methodology Virtuoso (ICADVM18.1) 引入了Virtuoso RF 解决方法，用户可以利用新的封装设计功能在Virtuoso 内部生成模块，进行封装。
- 12 Dec 2018
Digital Design: ECO with Stratus HLS and the Digital Implementation Flow

dpursley

For years chip designers have dealt with ECO’s when their source code was written in RTL. But the move to high-level synthesis (HLS) means that their source code is now one step further removed from the gate level netlist. This naturally leaves a question, “What if I need an ECO on my Stratus project?”

First and foremost, it’s important to understand that ECO’s are less common in the HLS flow. I’ll explain…
- 12 Dec 2018
Breakfast Bytes: The Conway Disappearance Effect

Paul McLellan

Over Thanksgiving weekend, Lynn Conway sent me a link to an article that she'd written for the October edition of IEEE Computer, The Disappeared: Beyond Winning and Losing. Mead & Conway When I interviewed Rob Rutenbar when he received last y...
- 12 Dec 2018
Breakfast Bytes: IEDM: All About Interconnect

Paul McLellan

The first week of December means it is IEDM, the International Electron Devices Meeting. This meeting pre-dates the integrated circuit and nearly pre-dates the transistor, so "electron devices" had a different meaning. In recent decades, th...
- 11 Dec 2018

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