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Latest Blog Posts

  • Spectre Tech Tips: Spectre X の大容量回路シミュレーション

    カスタムIC/ミックスシグナル: Spectre Tech Tips: Spectre X の大容量回路シミュレーション

    Custom IC Japan
    Custom IC Japan
    私は、特に EMIR 解析などでは、Spectre X を使用して非常に大規模なデザインをシミュレートするのに慣れています。通常、これらのデザインには、最大で数億のノード、数百万の MOSFET デバイス、および数億の寄生抵抗と容量が存在します。一連のシミュレーションには、回路の動作と、実行された EMIR 解析にもよりますが、数日間を要します。 それにもかかわらず、最近、抽出後のスタンダードセルベースの膨大なデジタルデザインを入手し、通常の過渡 (非 EMIR) 解析を実行して Spectre...
    • 10 May 2023
  • Cadence Tools Paving the Way for the AI-at-the-Edge Transition

    Corporate News: Cadence Tools Paving the Way for the AI-at-the-Edge Transition

    Vinod Khera
    Vinod Khera
    For machines to sense and replicate human intelligence, we must empower them with quick decision-making abilities for reliable operations even during adverse conditions. AI at the edge reduces latency by processing data generated by sensors/IoT devic...
    • 10 May 2023
  • TSMC Technology Roadmap, 2023 Version

    Breakfast Bytes: TSMC Technology Roadmap, 2023 Version

    Paul McLellan
    Paul McLellan
    April brings one of the two times during the year that TSMC lays out its process roadmap, fab construction plans, and more at the TSMC Technology Symposium. The other is the Open Innovation Platform Ecosystem Forum in October, usually just refer...
    • 8 May 2023
  • What Is Zonal Architecture? And Why Is it Upending the Automotive Supply Chain?

    Breakfast Bytes: What Is Zonal Architecture? And Why Is it Upending the Automotive Supply Chain?

    Paul McLellan
    Paul McLellan
    Earlier this week I wrote about the electric vehicle (EV) transition, how it is happening faster than many companies are prepared for, and the implications for the massive amount of change that the automotive companies have to accomplish (see my pos...
    • 5 May 2023
  • High-Fidelity CFD Mesh Generation With Voronoi Diagram

    Computational Fluid Dynamics: High-Fidelity CFD Mesh Generation With Voronoi Diagram

    Veena Parthan
    Veena Parthan
    We are attuned to the fact that the law of nature, or nature’s rule, drives various scientific phenomena. Comparable is the case with Voronoi geometries. These geometries are widely seen in beehives, human epidermal cells, and bones. What if these geometries can be applied to Computational Fluid Dynamics (CFD) for high-fidelity meshes?
    • 4 May 2023
  • maxon Is Perfecting Its Motors with Fidelity CFD

    Corporate News: maxon Is Perfecting Its Motors with Fidelity CFD

    Tanushri Shah
    Tanushri Shah
    maxon’s electric motors are magnetically close to perfect. Its motors are used in a wide variety of fields, from industrial applications to space technology. To optimize the motors, the maxon team is using Cadence tools. During the transfer of ...
    • 4 May 2023
  • Pre and Post-Silicon Verification Have Never Been Closer! Leveraging Portable Stimulus for Automatic Test Equipment (ATE)

    Verification: Pre and Post-Silicon Verification Have Never Been Closer! Leveraging Portable Stimulus for Automatic Test Equipment (ATE)

    Moshik Rubin
    Moshik Rubin

    The initial focus of the Portable Test and Stimulus Standard (PSS) was pre-silicon verification – even if the community, from the beginning, envisioned re-using pre-silicon test content in post-silicon. In this blog post, we will cover new use cases with PSS toward ATE: i.e., Automated Test Equipment typically used in production tests.

    The Challenge

    The ever-increasing design complexity of technology nodes and new…

    • 4 May 2023
  • Low-Power IC Design: What Is Required for Verification and Debug?

    Verification: Low-Power IC Design: What Is Required for Verification and Debug?

    Rich Chang
    Rich Chang
    Low-Power Design Techniques Are Needed In today’s world, energy saving is a hot topic. All kinds of devices are pursuing low-power consumption to be ecofriendly or to lower the operating costs. To address these goals, chip designs today have to...
    • 3 May 2023
  • Rohit Paliwal - Hardworking Lad With a Clear Vision

    The India Circuit: Rohit Paliwal - Hardworking Lad With a Clear Vision

    Asim Khan
    Asim Khan
    Each year, the Cadence Scholarship Program gives scholars a platform to fulfill their dreams and goals without letting their financial instability impede their progress. Subsequent to my previous blogs about the Cadence Scholarship Program, I bring t...
    • 2 May 2023
  • The Role of AI and ML in Electronic Design

    Corporate News: The Role of AI and ML in Electronic Design

    Corporate
    Corporate
    Join us for the second episode of our The Future of Electronics podcast as we talk to Paul Cunningham, Senior Vice President and General Manager at Cadence, about the transformative role of artificial intelligence and machine learning (AI/ML) in elec...
    • 2 May 2023
  • BoardSurfers: A Deep Dive Into the Print Functions in SKILL

    System, PCB, & Package Design : BoardSurfers: A Deep Dive Into the Print Functions in SKILL

    Kirti Sikri
    Kirti Sikri
    The ability to display the output is a crucial aspect of programming languages. The print functions enable programmers to display output in the form of text, numbers, and other data at the console or store it in a file, which helps in debugging, test...
    • 2 May 2023
  • The Automotive Electric Vehicle Transition

    Breakfast Bytes: The Automotive Electric Vehicle Transition

    Paul McLellan
    Paul McLellan
    The only really interesting part of the automotive industry is the electric vehicle (EV) segment. These vehicles are also called NEVs in China for "new energy vehicles". The reason that I say this is the only interesting segment is because it is clea...
    • 1 May 2023
  • Voltus Voice: Voltus-Celsius Integration for System Analysis —The Super Simple Way

    Digital Design: Voltus Voice: Voltus-Celsius Integration for System Analysis —The Super Simple Way

    Anshika Gahlaut
    Anshika Gahlaut
    Learn how the Voltus-Celsius integrated solution can help you achieve faster system-level thermal and power integrity analysis and closure.
    • 28 Apr 2023
  • デザインの階層化 - 善か悪か?

    カスタムIC/ミックスシグナル: デザインの階層化 - 善か悪か?

    Custom IC Japan
    Custom IC Japan
    By Girish Vaidyanathan, Sr. Product Manager, Virtuoso Studio, Cadence 類似したデザイン構成に対して、分割してグループ化をすることで、設計者は大規模データをより早く・簡単に把握することができます。また、このようなグループに対して命名規則を用いることで、必要な情報に対して容易にアクセスすることができます。回路設計者は、このような考え方を設計データの管理に利用しています。 大きなサブシステムを機能ベースにブロック分割するのも同じ目的...
    • 27 Apr 2023
  • Six Steps to Advance Your Career

    Corporate News: Six Steps to Advance Your Career

    Karna Nisewaner
    Karna Nisewaner
    Career advancement is an integral part of an individual’s professional journey. It is an indicator of development and takes many forms. Improved skills, additional scope, and new responsibilities are among the factors that lead to career advanc...
    • 27 Apr 2023
  • Planning a Long Drive this Summer? A Look Behind the Safety of Your Car’s Electronics

    Digital Design: Planning a Long Drive this Summer? A Look Behind the Safety of Your Car’s Electronics

    Neha Joshi
    Neha Joshi

    We know you are particular about your road safety while driving your automobile. And, of course, you should be!

    But for the car makers and us, the functional safety of the chips in your automobile is a top priority. Why?

    Functional safety activities start at the beginning of a product's development cycle. It's like raising a kid—you must start teaching them good habits when they're young, so they don't grow up as a safety…

    • 27 Apr 2023
  • Richard Goering, 1952-2023

    Breakfast Bytes: Richard Goering, 1952-2023

    Paul McLellan
    Paul McLellan
    I have some sad news to report. Richard Goering passed away last month at the age of 71. For many years, during the heyday of EE Times, Richard was the chief journalist covering EDA. As a marketing guy in EDA at various times, I interacted with Richa...
    • 27 Apr 2023
  • Cadence Demonstrates 112G-ELR SerDes IP on TSMC’s 3nm Process Technology

    SoC and IP: Cadence Demonstrates 112G-ELR SerDes IP on TSMC’s 3nm Process Technology

    Vinod Khera
    Vinod Khera

    The 3nm wave of technology is here! Cadence is proud to demonstrate its 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s 3nm (N3E) process technology at the TSMC 2023 North America Technology Symposium this week. This is the latest addition to the Cadence 112G-ELR SerDes IP family. Riding the wave of More than Moore, FinFET transistors keep shrinking in TSMC’s 3nm process as they move towards system-in-package…

    • 26 Apr 2023
  • Benchmarking Cadence Tools on Arm-Based Servers in the Cloud

    Cloud: Benchmarking Cadence Tools on Arm-Based Servers in the Cloud

    Vinod Khera
    Vinod Khera
    Arm is at the heart of the world’s most advanced digital products; over 70% of the world’s population uses Arm processor technology. The most innovative applications, from sensors to supercomputers (Fugaku) and servers to the cloud, are p...
    • 26 Apr 2023
  • How to Maximize Productivity and Lower Cost for Enterprise Prototyping

    Verification: How to Maximize Productivity and Lower Cost for Enterprise Prototyping

    Reela Samuel
    Reela Samuel
    Semiconductor chips are often produced as application-specific integrated circuits (ASICs) for high-volume electronic devices. It is critical to ensure high quality to avoid the added costs of finding and fixing bugs and remanufacturing the ASIC chi...
    • 25 Apr 2023
  • Spectre Tech Tips: Spectre X High-Capacity Circuit Simulation

    Analog/Custom Design: Spectre Tech Tips: Spectre X High-Capacity Circuit Simulation

    Stefan Wuensche
    Stefan Wuensche
    This blog discussed the experience of simulating a 400 million node design with SpectreX.
    • 25 Apr 2023
  • Training Insights Webinar: Introduction to the Genus iSpatial Synthesis Flow: Registrations Open

    Digital Design: Training Insights Webinar: Introduction to the Genus iSpatial Synthesis Flow: Registrations Open

    Neha Joshi
    Neha Joshi

    What Is this Webinar About?

     Please join me, Neha Joshi, Sr. Principal Education Application Engineer, for this free Cadence technical training webinar.

    With advanced-process nodes, a standard cell's physical delay, net delay, and congestion lead to a higher netlist requirement. Do you want to tackle congestion and achieve a better PPA for your design? If so, it's time to gear up with the Cadence Genus iSpatial Synthesis…

    • 24 Apr 2023
  • Would You Care for Some CFD with That Pi?

    Computational Fluid Dynamics: Would You Care for Some CFD with That Pi?

    John Chawner
    John Chawner
    I [ed. Travis Carrigan] can find inspiration for projects just about anywhere. While many ideas are fleeting and only grab enough attention for a day or two of work, some stick around and snowball into interesting projects. This is a look at one of t...
    • 24 Apr 2023
  • Last Week at Fidelity CFD

    Computational Fluid Dynamics: Last Week at Fidelity CFD

    John Chawner
    John Chawner
    Wow. By all accounts, CadenceCONNECT CFD and CadenceLIVE Silicon Valley last week were great events. We had a super line-up of speakers including a keynote from McLaren (hope you got to see their car and experience their simulator in the Designer Exp...
    • 24 Apr 2023
  • CadenceLIVE Silicon Valley 2023

    Breakfast Bytes: CadenceLIVE Silicon Valley 2023

    Paul McLellan
    Paul McLellan
    Last week was CadenceLIVE Silicon Valley, held at the Santa Clara Convention Center, and took place, as usual, over two days. It was very well attended and everywhere seemed fairly crowded. The structure of CadenceLIVE was that the first morning was ...
    • 24 Apr 2023
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