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Latest Blog Posts

  • Virtuoso Studio - 進化するアナログ設計

    カスタムIC/ミックスシグナル: Virtuoso Studio - 進化するアナログ設計

    Custom IC Japan
    Custom IC Japan
    By Steven Lewis, Product Management Director, Custom Product Group, Cadence 科学的には、恐竜は約6500万年前に絶滅したと言われています。それがアナログ設計とどう関係があるのか、つまり、椅子からおりたときに6500万歳を感じる以外に?まあ、一般に信じられているのとは違って、恐竜は生き続けていたのです。というのも、大学時代から、アナログ設計への感謝と魅力のために、私は恐竜の烙印を押されてきたからです。誰がアナログを研究する...
    • 20 Apr 2023
  • Virtuoso Studio : 適切なジョブのための最適なツール

    カスタムIC/ミックスシグナル: Virtuoso Studio : 適切なジョブのための最適なツール

    Custom IC Japan
    Custom IC Japan
    By Sravasti Nair, Product Engineering Group Director, and Girish Vaidyanathan, Sr. Product Manager それぞれのジョブに最適なツールを選択することは、アナログミックスシグナル設計の課題に対応し成功するためのスローガンです! アナログミックスシグナル設計は複雑な作業であり、例えばアナログ環境でのデジタルブロックの関与など、考慮すべき要素が多数あります。これらデジタルブロックのいくつかは再帰的で、一部のパ...
    • 20 Apr 2023
  • Leverage CFD to Predict, Model, and Mitigate Tsunamis for a Safer Tomorrow

    Computational Fluid Dynamics: Leverage CFD to Predict, Model, and Mitigate Tsunamis for a Safer Tomorrow

    Veena Parthan
    Veena Parthan
    CFD tools can help predict and model the generation, propagation, and mitigation of tsunamis for a safer tomorrow, targeting the safety of the inhabitants and building clusters around the coastal regions.
    • 20 Apr 2023
  • メッシュ解像度: 粗い、中間、細かいの新たな基準

    CFD(数値流体力学): メッシュ解像度: 粗い、中間、細かいの新たな基準

    CFD Japan
    CFD Japan
    第2回AIAA Geometry and Mesh Generation Workshopでは、2030年のCFDのビジョンに向けて、時代の流れに合った定量的な定義を採用することで、メッシュ解像度から定性的なものを取り除きました。 メッシュ解像度について質問されたとき、「ああ、粗いメッシュですね」と答えたことがありますか?しかし、それは何に対して粗いのでしょうか? 粗い、細かいとかいう言葉は、普通の状態から見た相対的な表現として使用されます。しかし、この普通とはどんな状態でしょうか? 各産業分野...
    • 19 Apr 2023
  • The AMD EPYC Performance Advantage for Cadence EDA Software

    Corporate News: The AMD EPYC Performance Advantage for Cadence EDA Software

    Corporate
    Corporate
    AMD is a leading semiconductor company driving innovation in high-performance computing, graphics, and visualization technologies. Their EPYC server processor family is designed to perform well on many different workloads, including high-perform...
    • 19 Apr 2023
  • Virtuoso Studio—The Evolution of Analog Design

    Corporate News: Virtuoso Studio—The Evolution of Analog Design

    Corporate
    Corporate
    By Steven Lewis, Product Management Director, Custom Product Group, Cadence Science says the dinosaurs were wiped out about 65 million years ago. What does that have to do with analog design, I mean, besides me feeling 65 million years old when I get...
    • 19 Apr 2023
  • Streamlining Your Verification Environment with Xcelium ML

    Verification: Streamlining Your Verification Environment with Xcelium ML

    Anika Sunda
    Anika Sunda
    When it comes to projects that involve cover groups and properties, and tests that utilize randomization, it can be challenging to ensure that the desired coverage goals are achieved. Coverage merging involves combining the coverage data generated fr...
    • 19 Apr 2023
  • Cadence、日月光、中原大學工業工程學系三方攜手教育訓練課程 共同培育半導體3D-IC人才

    Spotlight Taiwan: Cadence、日月光、中原大學工業工程學系三方攜手教育訓練課程 共同培育半導體3D-IC人才

    candyyu
    candyyu
    半導體產業是電子產業的最上游,也是最重要的支柱。台灣半導體產業實力舉世聞名,以晶圓製造為核心,上游IC設計自成體系,更延伸至下游的封裝測試,發展出全球絕無僅有、上下游整合非常完整的半導體產業聚落。隨著半導體前段生產製程的技術行進步伐放緩、晶片尺寸微縮有其極限,產業的注意力開始往封裝轉移,來延續半導體產業的持續成長。各大半導體廠紛紛轉向系統整合端 / 封裝端的創新,例如異質整合與Chiplet技術、系統級封裝(System in Package, SiP)取代SoC、2.5D & 3D-I...
    • 19 Apr 2023
  • BoardSurfers: The Power of Nesting Stackup Zones

    System, PCB, & Package Design : BoardSurfers: The Power of Nesting Stackup Zones

    Dhruv Prakash
    Dhruv Prakash
    In the world of PCB design, the term stackup refers to the arrangement of different layers of materials that make up the board. These layers include the conductive and insulating layers and other components, such as vias and planes. A stackup is an ...
    • 18 Apr 2023
  • Cadence, ASE Group, and Chung Yuan Christian University Collaborate on Education and Training Program to Cultivate Talent for 3D-IC Design

    Academic Network: Cadence, ASE Group, and Chung Yuan Christian University Collaborate on Education and Training Program to Cultivate Talent for 3D-IC Design

    Tracy Zhu
    Tracy Zhu
    The semiconductor industry is an important pillar of the overarching electronics ecosystem. The strength of Taiwan's semiconductor industry is world-renowned, with wafer manufacturing at the core, upstream IC design as a self-contained system, an...
    • 18 Apr 2023
  • DEI@Cadence: Phenomenal Women at CWC India

    Life at Cadence: DEI@Cadence: Phenomenal Women at CWC India

    Jonaki
    Jonaki
    Cadence Women Conference (CWC) India celebrated the success and achievements of women at Cadence as well as provided an opportunity to grow, learn and network, and think about contributing to the women in technology community.
    • 18 Apr 2023
  • Lightelligence Accelerates DFT Simulation Using Cadence Xcelium Multi-Core

    Verification: Lightelligence Accelerates DFT Simulation Using Cadence Xcelium Multi-Core

    Reela Samuel
    Reela Samuel
    The growing design complexity of today’s system on chips can result in long hours, days, and even weeks of design for testability (DFT) simulations. As these tend to occur at the end of an application-specific integrated circuit (ASIC) project,...
    • 17 Apr 2023
  • Cadence Achieves AWS Manufacturing and Industrial Competency

    Cloud: Cadence Achieves AWS Manufacturing and Industrial Competency

    SarahAdams
    SarahAdams
    We here at Cadence are excited to share some recent news regarding our cloud-based offerings—we have achieved the Amazon Web Services (AWS) Manufacturing and Industrial Competency. This designation recognizes Cadence for its expertise in provid...
    • 17 Apr 2023
  • Digital Implementation Education Kit is Ready for Download!

    Academic Network: Digital Implementation Education Kit is Ready for Download!

    Anton Klotz
    Anton Klotz
    www.youtube.com/watch What is the difference between analog and digital EDA tools for backend implementation? While analog designers could theoretically do polygon pushing to place single devices and draw the routing manually, it is very cumbersome a...
    • 16 Apr 2023
  • School for the Underprivileged Inaugurated - A CSR Initiative of Cadence India

    The India Circuit: School for the Underprivileged Inaugurated - A CSR Initiative of Cadence India

    Asim Khan
    Asim Khan
    Giving back to the communities is a core part of our history and culture. We have several Corporate Social Responsibility (CSR) programs, including in education, all of which are creating a positive impact in society. We are committed to providing un...
    • 14 Apr 2023
  • Virtuosity: Voltus-XFi Custom Power Integrity Solutionで EM-IR 解析を加速

    カスタムIC/ミックスシグナル: Virtuosity: Voltus-XFi Custom Power Integrity Solutionで EM-IR 解析を加速

    Custom IC Japan
    Custom IC Japan
    アナログブロックとカスタムブロックのエレクトロマイグレーションと IRドロップを3倍またはそれ以上の速さでサインオフしましたか? 「はい!」 - それは正しい回答です。これは、Cadence Voltus-Fi から Cadence Voltus-XFi Custom Power Integrity Solution にアップグレードした後の生産性の向上について、一部のお客様が述べていることです。 エレクトロマイグレーションおよびIRドロップ (EM-IR) 解析はツールではありません。実際には...
    • 13 Apr 2023
  • Spectre Tech Tips: Spectre EMIRの一般的な問題への対処方法

    カスタムIC/ミックスシグナル: Spectre Tech Tips: Spectre EMIRの一般的な問題への対処方法

    Custom IC Japan
    Custom IC Japan
    Voltus-XFiのシミュレーションエンジンであるSpectre EMIRは、IRドロップとEM電流の解析を行うことができます。ユーザーから報告された問題を検証したところ、Spectre EMIRの問題の多くは、適切な準備とセットアップによって回避できることが判明しました。Spectre EMIRユーザーから報告される最も一般的な問題は、イタレーション手法のEMIR結果を、ゴールデンとなるダイレクト手法と比較した際の、IRドロップとEM電流の不正確さです。 多くの場合、これらの精度の問題は、不...
    • 13 Apr 2023
  • The Future of Electronics: New Podcast

    Corporate News: The Future of Electronics: New Podcast

    Corporate
    Corporate
    The "Designed with Cadence" series now has a podcast, and it’s all about cutting-edge technology and innovation across the EDA industry. Hosted by Jeff Applebaum of Cadence, each episode will feature various industry leaders from Cade...
    • 13 Apr 2023
  • 4nm 112G-ELR SerDes PHY IP

    Breakfast Bytes: 4nm 112G-ELR SerDes PHY IP

    Paul McLellan
    Paul McLellan
    That's a lot of buzzwords! I assume you already know that SerDes stands for serializer-deserializer. It is an IP block that takes parallel data from buses on the chip and transforms it into a very high-frequency serial signal. In this case, the s...
    • 13 Apr 2023
  • Multiphysics In-Design Analysis Track at CadenceLIVE 2023 Showcases Design Solutions for Chip, Package, and Board Applications

    System, PCB, & Package Design : Multiphysics In-Design Analysis Track at CadenceLIVE 2023 Showcases Design Solutions for Chip, Package, and Board Applications

    Jojo Chang
    Jojo Chang
    Cadence provides a unified, integrated, and collaborative design environment to help engineers confidently deliver more productive outcomes. Join our Multiphysics In-Design Analysis track at CadenceLIVE Silicon Valley on April 20 to explore how our simulation and analysis software empowers customers to solve complex electromagnetic, thermal, and electromechanical challenges in electronic system designs from concept through…
    • 12 Apr 2023
  • Printing Grids in 3D

    Computational Fluid Dynamics: Printing Grids in 3D

    John Chawner
    John Chawner
    Those of you who attended the 2011 Pointwise User Group Meeting may remember that our company president, John Chawner, mentioned during his closing statements how nice it would be to have the ability to print your grids in 3D. That was more than just...
    • 11 Apr 2023
  • 2023年3月リリース、OrCAD / Allegro 22.1 HotFix 003の新機能ハイライト

    PCB設計/ICパッケージ設計: 2023年3月リリース、OrCAD / Allegro 22.1 HotFix 003の新機能ハイライト

    SPB Japan
    SPB Japan
    OrCAD® 及び Allegro® 22.1のHotFix 003 (QIR2)アップデートが Cadence Downloads からダウンロード可能になりました。本ブログでは、このリリースにアクセスするための重要なリンクと、主要な機能変更や新機能についての概要をご紹介します。     OrCAD/Allegro 22.1 (SPB221) 以下、主要な機能変更や新機能のリストとその簡単な概要を、プロダクト毎にご紹介します。 Allegro...
    • 10 Apr 2023
  • Accuracy, Convergence, and Mesh Quality

    Computational Fluid Dynamics: Accuracy, Convergence, and Mesh Quality

    John Chawner
    John Chawner
    This article was first published in June 2012. It was so popular there it's reposted here to reach a broader audience. “We know embarrassingly little about how the mesh affects the CFD solution,” said Prof. Carl Ollivier-Gooch of the ...
    • 10 Apr 2023
  • Glyph API for Python in Fidelity Pointwise

    Computational Fluid Dynamics: Glyph API for Python in Fidelity Pointwise

    John Chawner
    John Chawner
    Ever wish you could write Glyph scripts to extend or customize the functionality of Cadence's Fidelity Pointwise software in some language other than Tcl/Tk? Python coders: wish no more! In conjunction with the release of Pointwise V18....
    • 10 Apr 2023
  • The 50th Anniversary of Picasso's Death

    Breakfast Bytes: The 50th Anniversary of Picasso's Death

    Paul McLellan
    Paul McLellan
    Today, 8th April 2023, is the 50th anniversary of the death of Picasso. He died on 8th April 1973 at the age of 91 in Mougins, France. Mougins is a famous village in the south of France, not far from Cadence's office in Sophia Antipolis. It is famous...
    • 8 Apr 2023
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