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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Verification

Xilinx Zynq-7000 Virtual Platform Performance: Native Linux vs. VirtualBox

In my last blog post , I covered three frequently asked questions about using the…

• 5 min read
taskset , virtual platforms , Unity 2D , System Development Suite , embedded software , VSP , Ubuntu , VirtualBox , virtual prototype , Virtual Machine , Linux vs VirtualBox , Unity3D , xilinx , graphics , linux , Zynq-7000 , simulation , ESL , System Design and Verification

Verification

Xilinx Zynq-7000 Virtual Platform Frequently Asked Questions: VirtualBox Edition

The use of virtual machine technology offers great ease of use benefits. Since the…

• 7 min read
VBoxManage , port forwarding , network address translation , eclipse , virtual platforms , NAT , virtual prototypes , embedded software , Xilinx SDK , Ubuntu , VirtualBox , system design , Virtual Machine , FAQ , System Design & Verification , xilinx , Zynq virtual platform , Zynq-7000 , ESL

Digital Design

Five-Minute Tutorial: Understanding the Encounter Power System (EPS) Reports Dir…

No matter how you run your power analysis - with Encounter Power System (EPS) or…

• 3 min read
EDI , rail analysis , EPS reports , tutorial , encounter digital implementation system , EPS , encounter , digital implementation , IRdrop , Power Analysis , powergrid view , EM , five-minute , encounter power system , electromigraion

Analog/Custom Design

What is Digitally Assisted Analog Design?

Mixed-signal applications are among the fastest growing segments in the electronics…

• 2 min read
daa , AMS , Low Power , mixed signal design , mixed signal solution , Mixed-Signal , dac2012 , Mixed signal physical implementation , mixed signal , cortex M , DAC 2012 , ARM , boris murmann , digitally assisted analog , mixed-signal verification

System, PCB, & Package Design 

What's Good About Allegro Via Patterns During Group Routing? See for Yourself in…

New to the 16.5 release of Allegro PCB Editor is the ability to establish via patterns…

• 3 min read
PCB , PCB Layout and routing , blind vias , diff pairs , inset vias , global route , Routing , staggered vias , layer stacks , Allegro 16.5 , SPB , via rules , PCB Editor , High-Density Interconnect , Layout , via , via patterns , design , vias , "PCB design" , PCB design , SPB16.5 , Allegro PCB Editor , differential pairs , group routing , Differential Pair Support , buried vias , HDI , PCB Capture , Allegro

Verification

My Constraint was Ignored – Is it a Tool Bug? IntelliGen Gen Debugger Can Help!

The IntelliGen Gen Debugger is a powerful Specman tool that can debug any generation…

• 4 min read
AF , IntelliGen , Specman , debug , Functional Verification , Gen debugger , test generation , Gen , Generation , e language , Constraints , constraint not enforced , verification

System, PCB, & Package Design 

What's Good About OrCAD Capture’s Find Result Report? Look to SPB16.5 and See!

The OrCAD Capture 16.5 release now has a method to generate a report (in CSV or HTML…

• 1 min read
PCB , capture , "capture CIS" , Allegro Design Entry , Design Entry CIS , OrCAD Capture Marketplace , Find command , OrCAD Capture , Capture CIS , Capture-CIS , Allegro 16.5 , SPB , Find result , design , OrCAD , PCB design , Design Entry , SPB16.5 , PCB Capture , Schematic , OrCAD reports

System, PCB, & Package Design 

What's Good About ADW’s Generic Models? Check out the 16.5 Release and See!

The 16.5 release of Allegro Design Workbench ( ADW ) provides support for generic…

• 1 min read
PCB , generic models , Allegro Design Workbench , Library flow , Allegro 16.5 , Library and design data management , design data management , design , "PCB design" , PCB design , SPB16.5 , Librarians , library , ADW , Allegro

Verification

Analyzing Error Reports When Specman Crashes

One of the most frustrating events while running a tool would be to experience a…

• 8 min read
AF , SystemVerilog , Specman , OVM ML , Functional Verification , Testbench simulation , OVM e , EDA , e , stack trace , Signal Integrity , e language , team specman , Aspect Oriented Programming , eRM , specman crashes , simulation , AOP , IES-XL

Verification

Video: “Drive For Innovation” Finds It At Every Turn

With some notable exceptions, too often technology trade press reporting has been…

• less than a min read
Brian Fuller , Avenet Express , Joe Hupcey III , innovation , "Drive for Innovation" , UBM Electronics , Chevy Volt , EE Times

Verification

Modeling Large Memories in SystemC

Sometimes Virtual Platforms model systems with large amounts of memory. Many embedded…

• 3 min read
zynq , Memory , virtual platforms , TLM , virtual prototypes , SDRAM , Verilog , SystemC memories , SystemC , memory models , modeling memories , linux

Verification

Lessons from CDNLive! India Best Paper -- Property Driven Simulation in IEV

Recently the CDNLive! India 2011 best paper award winner, "Complex IP Verification…

• 2 min read
ABV , CDNLive India , Vinaya Singh , Formal Analysis , NVIDIA , ADS , property-driven simulation , CDNLive! , IEV , Assertion-Driven Simulation , Formal verification , India , Assertion-based verification

Analog/Custom Design

CDNLive! -- Real Number Model Development and Application in Mixed-Signal SoC Ve…

With the escalating complexity of analog mixed-signal (AMS) chips, increasing digital…

• 3 min read
real number modeling , CDN Live , CDNLive SV 2012 , CDNLive , AMS Designer , LSI , RNM , behavioral models , CDNLive! , wreal , Luo , Virtuoso environment , AMS Verification , mixed-signal verification , verification

Digital Design

When One Via Just Doesn’t Cut It – Recommended Settings for NanoRoute Including Multi…

Maximizing the usage of Multi-cut vias by the router is one key to improving yield…

• 2 min read
EDI , EDI system , 28nm , EDI 11.1 , NanoRoute , encounter , via , digital , Digital Implementation , multi-cut via insertion , Brian Wallace , EDI 11 , DFM , "SoC-Encounter"

Analog/Custom Design

Things You Didn't Know About Virtuoso: Change is Here to Stay

Speaking of variation -- and isn't everyone these days -- something strikes me in…

• 4 min read
Variability Aware Design , Analog Design Environment , Virtuoso IC6.1.5 , custom/analog , IC 6.1 , Analog Simulation , IC615 , analog , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , variability , Virtuoso , ADE-GXL , Analog Design Environment , ADE-XL , Variation , IC 6.1.4 , Custom IC Design , change

System, PCB, & Package Design 

What's Good About Selection Filters in DEHDL? The Secret's in the 16.5 Release!

In the 16.5 release of Design Entry HDL (DEHDL) -- Cadence Online Support access…

• 1 min read
PCB , DEHDL , selection filters , property changes , Allegro 16.5 , Design Entry HDL , design , PCB design , 16.5 , Design Entry , SPB16.5 , ConceptHDL , PCB Capture , Schematic , Allegro

Verification

Trying to Make Sense of the Chaos – Impressions from Design West 2012

Walking the show floor of "Design West," the show formerly known as "Embedded Systems…

• 3 min read
SysML , Intel , Embedded Systems Conferences , software development tools , chaos , OS , embedded software , UML , Test , Design West , software , ARM , embedded systems , operating systems

Analog/Custom Design

DVCon 2012: Bringing Continuous Domain into SystemVerilog Covergroups

On the last day of February 2012, I presented a proposal at the DVCon 2012 Conference…

• 2 min read
SystemVerilog , coverage , covergroups , Functional Verification , analog , Mixed-Signal , DVcon , real number types , functional coverage , mixed signal , floating point , mixed-signal verification , verification , real number

System, PCB, & Package Design 

What's Good About PCB SI Signal Integrity Bus Analysis? Allegro 16.5 Has a Few New…

Address Bus Topology Support Part of the setup for Bus Analysis in Allegro PCB SI…

• 2 min read
PCB SI , PCB , SI , diff pairs , Signal Intregrity , SI bus analysis , SigXP UI , PCB Signal and power integrity , "PCB SI" , Allegro 16.5 , SPB , Signal Integrity , PCB Signal integrity , Allegro PCB SI , PCB design , SPB16.5 , differential pairs , SI analysis and modeling , Differential Pair Support , Allegro
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