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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Analog/Custom Design

Virtuoso Video Diary: I Am Not Promoting Layout Hierarchy Manipulation!

Are you contemplating manipulating your layout hierarchy by adding or removing a…

• 5 min read
Flatten , Transparent instances , Virtuoso Video Diary , Connectivity-driven , Make Cell , XL-compliance , Layout hierarchy manipulation , Custom IC Design , Virtuoso Layout Suite XL

Breakfast Bytes

The Amazing Raspberry Pi Story

Eben Upton gave a spellbinding keynote at ARM TechCon on the history of Raspberry…

• 9 min read
BBC , Raspberry Pi , Cambridge , acorn , british broadcasting corporation , ARM , Breakfast Bytes

Breakfast Bytes

Automotive Security: A Hacker's Eye View

Charlie Miller gave a keynote at ARM TechCon on automotive security. He is regarded…

• 8 min read
security , Automotive , onstar , uber , jeep , chris valasek , charlie miller , tesla , wired magazine , Breakfast Bytes

Verification

Analog Devices Promotes Portable Stimulus at DVClub

If you’re not familiar with the series of DVClub events held in North American, Europe…

• 3 min read
Analog Devices. ADI , pswg , cadence , debug , System Design and Verification , Dave Brownell , software , Accellera , System Design & Verification , portable stimulus , System Design and Verification , verification

Breakfast Bytes

What's For Breakfast? Video Preview November 7th to 11th

https://youtu.be/n4jz8shM1hM Monday: The amazing story of Raspberry Pi as…

• less than a min read
security , Automotive , greg yeric , ARM Techcon , Jasper User Group , Low Power , trustzone , Raspberry Pi , jasper gold , palladium z1 , eben upton , JUG , IoT , tcl1 , Palladium , Jasper , Mike Muller , medical , Internet of Things , Power Analysis , ISO 26262 , ARM , Formal verification

System, PCB, & Package Design 

How to Address the Challenges of Serial Link Design and Analysis

What is a serial link? It's an interface where data is serialized for high-speed…

• 3 min read
Serial link analysis , PCB , SI , IBIS-AMI , Signal Integrity , Sigrity , High Speed design , Allegro

Breakfast Bytes

Automotive Is a Pot of Gold Guarded by a Dragon

One of the big themes of pretty much any conference on semiconductors these days…

• 6 min read
Automotive , functional safety , tool confidence level , DVcon , DVCon Europe , ISO 26262 , optima , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Optimized FFTs on the Tensilica ConnX BBE32EP DSP

Fast Fourier transform (FFT) is a key kernel in almost all DSP applications, and…

• less than a min read
DSP , Whiteboard Wednesdays , baseband , ConnX , radar , Tensilica , signal processing , FFT

Verification

Genie in a Mouse Click: Indago Protocol Debug App

Do you remember what life was like before the internet and smart phones? If you wanted…

• 4 min read
Productivity Tool , Verification IP , and Verification IP' , VIP , Indago Protocol Debug App , design , 'Tensilica

Breakfast Bytes

Wave Computing: a Dataflow Processor for Deep Learning

On the first day of the Linley Processor conference someone told me that he was really…

• 4 min read
deep learning , tpu , wave computing , DPU , tensor flow , dataflow computing , Breakfast Bytes , dataflow processor

Breakfast Bytes

Segars and Son

When I was growing up, there was a TV show in the UK called Steptoe and Son, and…

• 5 min read
ARM Techcon , Simon Segars , IoT , masayoshi son , Internet of Things , arm holdings , ARM , Breakfast Bytes

Academic Network

Students from Tsinghua University Visit Cadence Beijing

On October 20, 2016, 12 Masters and Ph.D. students mostly from Institute of Microelectronics…

• less than a min read
Cadence Academic Network

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? Arc-aware routing with enhanced contour hug saves…

Enhanced Contour Routing is a new prototype feature in the Cadence® Allegro® PCB…

• 1 min read
Allegro 17.2 , Routing , Rigid-Flex , PCB design , Allegro PCB Editor , Why Move Up to 17.2

Breakfast Bytes

Automotive at Linley: Intelligent Vehicles and Intelligent Intersections

The whole afternoon the second day of the Linley Processor Conference was dedicated…

• 5 min read
Automotive , NXP , linley processor conference , tensilica vision , mike demler , Automotive Ethernet , Linley , autonomous vehicles , Breakfast Bytes

Breakfast Bytes

How Does Virtualization Work?

I wrote recently about the keynote from the Linley processor conference about network…

• 6 min read
Intel , virtualization , IBM , VMware , vm/370 , vm/cms , Breakfast Bytes

System, PCB, & Package Design 

How PCB Design Teams Can Signoff on a Predictable Schedule by Finding Signal Integrity…

Sigrity Tech Tips Series A major challenge for PCB design teams is how…

• 2 min read
PCB , pre-route analyzing , Signal Integrity , Sigrity , Allegro

Breakfast Bytes

What's For Breakfast? Video Preview October 31st to November 4th

https://youtu.be/wL43x-MOfWY It's Automotive Week on Breakfast Bytes. …

• less than a min read
Automotive , ARM Techcon , functional safety , NXP , softbank , deep learning , wave computing , linley group , DVcon , DVCon Europe , ISO 26262 , wired magazine , ARM , fusa , reliability

Breakfast Bytes

Sophia Antipolis

Sophia Antipolis is in the south of France, a sort of research park carved out of…

• 5 min read
vlsi technology , Intel , NXP , Infineon , Freescale , amadeus , Samsung , Bosch , dec , compass , Qualcomm , st ericsson , air france , sophia antipolis , Breakfast Bytes , digital equipment corporation

Breakfast Bytes

Make Sure Your Car Doesn't Break Too Often...When It Does, Make Sure You Catch I…

We need our cars to be safe as the amount of electronics in them increases almost…

• 6 min read
Automotive , functional safety , iso26262 , ISO 26262 , Breakfast Bytes , reliability
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