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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
cdns - all_blogs_categories

Blog - Post List

Latest blogs

Verification

Implementing User-Defined Register Access Policies with vr_ad and IPXACT

The register and memory package vr_ad for Specman is used in pretty much every verification…

• 2 min read
AF , Specman , debug , vr_ad , e code , Funcional Verification , Incisive Enterprise Simulator (IES) , ipxact

Whiteboard Wednesdays

Whiteboard Wednesdays - Leading Up to PCI Express 4.0

In this week's Whiteboard Wednesdays, Moshik Rubin discusses the history of the PCI…

• less than a min read
Whiteboard Wednesdays , IP , PCIe Gen4 , PCI Express

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Design Partitioning? 16.6 Has Several New Enhancements

The 16.6 release of Allegro PCB Editor has several new enhancements for team design…

• 3 min read
Allegro 16.6 , 16.6 , Team design , SPB , PCB Editor , Constraint Manager , Allegro PCB Editor

Whiteboard Wednesdays

Whiteboard Wednesdays - Using USB IP Controllers in Today's Devices

In this week's Whiteboard Wednesdays, Jacek Duda follows up on his earlier video…

• less than a min read
USB IP controllers , Whiteboard Wednesdays , USB controllers

Whiteboard Wednesdays

Whiteboard Wednesdays—Improving Power Optimization with PCI Express

In this week's Whiteboard Wednesdays video, Arif Khan takes a closer look at PCI…

• less than a min read
Whiteboard Wednesdays , PCIe , PCI Express , power optimization

System, PCB, & Package Design 

What's Good About Allegro PCB Editor IPC 2581 Data Transfer Standard? 16.6 Has It

The 16.6 Allegro PCB Editor now has IPC 2581 data transfer capabilities. Thanks to…

• 10 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , cadence , 16.6 , layer stacks , artwork , SPB , interfaces , PCB Editor , Layout , design , PCB design , Grzenia , Allegro PCB Editor , Standards based Interfaces , Allegro

Whiteboard Wednesdays

Whiteboard Wednesdays - Improving Hardware Verification with Accelerated Verification…

In this week's Whiteboard Wednesdays, Tom Hackett talks about Accelerated Verification…

• less than a min read
AVIP , accelerated VIP , Verification IP , Whiteboard Wednesdays , VIP , hardware verification

System, PCB, & Package Design 

Build Components Quickly and Easily with Pre-Defined Escape Routing Using Cadence…

When it comes to designing a dense flip-chip die - or even defining a BGA for a complex…

• 5 min read
Allegro package design , reusable tiles , EDA , package design , SiP Layout , substrate design tools

RF Engineering

Distortion Summary in New CDNLive YouTube Video and at IEEE IMS2014 Next Week!

Hi Folks, Check out this great new video on YouTube: CDNLive SV 2014: PMC Improves…

• less than a min read
Wilsey , Spectre RF , spectreRF , RF design , harmonic balance , Distortion

Verification

PCIe Gen4 LIVE Demo at PCI-SIG DevCon Next Week

The PCI-SIG has (FINALLY) released the PCIe 4.0 rev 0.3 specification for members…

• 1 min read
Verification IP , IP , PCI Express 3.0 , Gen3 , NVMe , VIP , M-PCIe , MPCIe , PCIe , PCIe Gen3 , PCI-SIG

Whiteboard Wednesdays

Whiteboard Wednesdays—Trends in the Mobile Memory World

In this week's Whiteboard Wednesdays, Kishore Kasamsetty discusses the low-power…

• less than a min read
Whiteboard Wednesdays , Memory , LPDDR4 , mobile , LPDDR3

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Offset Routing? 16.6 Has a Few New Enhancements

The Add Connect with Offset command in Allegro PCB Editor 16.6 is designed to primarily…

• 4 min read
Routing , signal grouping , 16.6 , SPB , PCB Editor , differential pair , Layout , group routing , Allegro

Verification

DAC 2014—ESL Design Is Dead... Long Live ESL!

Next week the EDA industry is getting together in San Francisco for Design Automation…

• 20 min read
DAC , Frank Schirrmeister , ESL

Analog/Custom Design

Virtuosity: 19 Things I Learned in April 2014 by Browsing Cadence Online Support

Plenty to keep you busy this month. Lots of RAKs, videos, and new Quick Start Guides…

• 4 min read
Variability Aware Design , AMS , Virtuoso online support , Routing , ADE XL , Virtuoso Analog Design Environment , Spectre , Schematic Editor , Virtuosity , Virtuoso Layout Suite XL

SoC and IP

IP at DAC? You Bet!

This year, the Design Automation Conference (June 1-5 in San Francisco) has put a…

• 1 min read
Verification IP , Design IP , VIP , DAC2014

RF Engineering

How to Specify Phase Noise as an Instance Parameter in Spectre Sources (e.g. vsource…

Last year, I wrote a blog post entitled Modeling Oscillators with Arbitrary Phase…

• 1 min read
Spectre RF , phase noise , spectreRF , analogLib , port , noise profiles

Whiteboard Wednesdays

Whiteboard Wednesdays - Taking Command of MIPI PHYs - M-PHY

In this week's Whiteboard Wednesdays, the second installment of a three-party series…

• less than a min read
mobile devices , Whiteboard Wednesdays , MIPI PHYs , M-PHY

SoC and IP

400G Task Force, 100G Backplane Project and Other Highlights from IEEE 802.3 Ethernet…

Here is another report from an IEEE 802.3 Ethernet standards meeting, this time held…

• 2 min read
25G Ethernet , Ethernet standards , Automotive Ethernet , IEEE 802.3 , 100G backplane , 400G

Computational Fluid Dynamics

NASA Glenn Research Center: Integrated Fluid Dynamics – Acoustics Simulation Approach…

An innovative computational approach, integrating mesh generation, CFD simultaneous…

• less than a min read
CDNS - Fix Layout Hompage