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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela Samuel
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

SoC and IP

400G Task Force, 100G Backplane Project and Other Highlights from IEEE 802.3 Ethernet…

Here is another report from an IEEE 802.3 Ethernet standards meeting, this time held…

• 2 min read
25G Ethernet , Ethernet standards , Automotive Ethernet , IEEE 802.3 , 100G backplane , 400G

Computational Fluid Dynamics

NASA Glenn Research Center: Integrated Fluid Dynamics – Acoustics Simulation Approach…

An innovative computational approach, integrating mesh generation, CFD simultaneous…

• less than a min read

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Show Measure for Dual Units? 16.6 Has It!

The Allegro PCB Editor 16.6 ‘Show Measure’ command now displays results in database…

• 1 min read
PCB , PCB Layout and routing , Allegro GUI , Allegro 16.6 , Routing , electrical constraints , SPB , PCB Editor , Layout , design , PCB design , physical layout design , Allegro PCB Editor , PCB Capture , Allegro

Analog/Custom Design

High Yield Analysis and Optimization - How to Design the Circuit to Six Sigma

Why high yield analysis? One failed memory cell out of millions cells will cause…

• 2 min read
Six Sigma , Virtuoso , Circuit Design , analog design , high yield analysis

Verification

sync and wait Actions vs. Temporal Struct and Unit Members

Using sync on a temporal expression (TE), does not guarantee that the execution will…

• 2 min read
AF , events , IntelliGen , Specman , units , e code , temporal expressions , Funcional Verification

Whiteboard Wednesdays

Whiteboard Wednesdays - Promises and Challenges of DDR4 Memory Technology

In this week's Whiteboard Wednesdays, Kishore Kasamsetty provides a history on DDR4…

• less than a min read
memory protocols , Whiteboard Wednesdays , DDR4 , DDR3

RF Engineering

See Cadence RF Technologies at IEEE International Microwave Symposium 2014

RF Enthusiasts, Come connect with Cadence RF experts and discover the latest advances…

• less than a min read
RF Simulation , IMS , RFIC , Spectre RF , Virtuoso , International Microwave Symposium , IEEE

SoC and IP

Don’t Miss Embedded Vision Summit West on May 29

Embedded Vision Summit West 2014 on May 29 at the Santa Clara Convention Center provides…

• less than a min read
Embedded Vision Summit , video , google , Facebook , Tensilica , vision , embedded vision technology , imaging

Whiteboard Wednesdays

Whiteboard Wednesdays - Verifying Your Designs with Simulation VIP

In this week's Whiteboard Wednesdays, Tom Hackett takes a closer look at simulation…

• less than a min read
Verification IP , VIP , design verification , simulation VIP , PCI Express , protocol checks

Verification

e and SystemVerilog: The Ultimate Race

For years we've watched the e and SystemVerilog race via countless presentations…

• 1 min read
IEEE 1647 , SystemVerilog , IEEE 1800 , simulation performance , e , Adam Sherer , UVM ML , Funcional Verification , IES

System, PCB, & Package Design 

Add a View of Your Package Substrate in Your IC Layout Tool for Maximum Design Context…

We have all heard about co-design, how it is going to get us to market on time, reduce…

• 4 min read
SiP , Allegro Package Designer , IC packaging documentation , APD 16.6 , SiP Layout

Analog/Custom Design

How Can You Learn About Mixed-Signal Verification and Implementation Flows at Your…

The vast majority of SoCs today are advanced mixed-signal designs. The old mixed…

• 3 min read
real number modeling , AMS Designer , EDA training , SV-RNM , DMS , mixed signal , Schematic Model Generator , RAKs

Whiteboard Wednesdays

Whiteboard Wednesdays—Wireless Transceiver Implementations

In this week's Whiteboard Wednesdays installment, Priyank Shukla highlights wireless…

• less than a min read
RF , wireless , Whiteboard Wednesdays , IP , 802.11x , digital , AFE , LTE

System, PCB, & Package Design 

What's Good About Allegro AMS Simulator PSpice Model Encryption? It’s in the 16.6…

With the 16.6 Allegro AMS Simulator (PSpice) release, you now have a new AES 256…

• less than a min read
AMS , Allegro 16.6 , AMS simulator , Allegro AMS , PSPICE , AMS simulation , model editor

Analog/Custom Design

What’s New in Virtuoso ADE XL in IC616 ISR6?

In a previous post, I explained the release model used for Virtuoso ADE and ViVA…

• 1 min read
Analog Design Environment , custom IC simulation , ADE XL , Virtuoso Analog Design Environment , Virtuoso , ADE-XL , Circuit Design , Custom IC Design , IC 6.1.6

RF Engineering

Broadband SPICE -- New Tool for S-Parameter Simulation in Spectre RF

Hi All, Here's another great new feature that I've found very helpful... Broadband…

• less than a min read
nport , Spectre RF , Broadband SPICE , nport settings , Spectre , s parameter simulation

RF Engineering

New Memory Estimator Helps Determine Amount of Memory Required for Large Harmonic…

Hi Folks, A question that I've often received from designers, "Is there a method…

• 1 min read
HB , Spectre RF , MMSIM , spectreRF , harmonic balance , memory estimator

Whiteboard Wednesdays

Whiteboard Wednesdays - Taking Command of MIPI PHYs

In this week's Whiteboard Wednesdays installment, Kevin Yee discusses what it means…

• less than a min read
mobile devices , Whiteboard Wednesdays , D-PHY , MIPI protocols , MIPI PHYs

Analog/Custom Design

Keeping Your Circuit in Tune: Sensitivity Analysis and Circuit Optimization

Anyone who has ever played a musical instrument knows how hard it can be to keep…

• 4 min read
Variability Aware Design , ADE GXL , worst case corners , optimization , Virtuoso , statistical corners , Variation
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