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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Verification

System-Level Design and the Waves of EDA

Before January comes to an end it is time for my annual flashback and brief reflection…

• 5 min read
virtual prototypes , IP integration , abstraction , VCC , VSI , IP assembly , cars , EDAC , software , automobiles , 1997 , Virtual Platforms , IEEE Spectrum , Schirrmeister , ESL , ESL system-level design

Verification

Incisive Performance Scales to Meet Advanced Node SoC Verification Requirements

Its’ all about RTL simulation. I mean gates. I mean turn-around-time. Project-level…

• 2 min read
verification speed , whitepaper , uvm , Low Power , gate level , simulation speed , Functional Verification , Incisive Enterprise Simulator , 20nm , Low-Power , Incisive , Mixed-Signal , gate-level , Incisive performance , Simulation acceleration , DVcon , testbench , Incisive Enterprise Simulator (IES) , simulation , IES , Assertion-based verification , IES-XL

Analog/Custom Design

Things You Didn't Know About Virtuoso: We've Got You Cornered

One of the big buzzwords around the EDA world these days is "variation." Don't you…

• 3 min read
Corners , Analog Design Environment , Virtuoso IC6.1.5 , custom/analog , IC615 , analog , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , Virtuoso , Analog Design Environment , ADE-XL , Custom IC Design , corner analysis

Verification

Video Killed the Reference Manual Star

[Preface: recall the melody of the Buggles' 1979 hit " Video Killed the Radio Star…

• 1 min read
ABV , videos , metric driven verification (MDV) , Functional Verification , Formal Analysis , ABVIP , formal , YouTube , SVA , PSL , assertions , Axel Scherer , MDV , IEV , Assertion-Driven Simulation , simulation , Formal verification , IFV , Assertion-based verification

Verification

UVM: "Everything that Can be Invented Has Been Invented" Not True!

Much like Charles Duell's famous 1899 quote**, the notion that the Universal Verification…

• 1 min read
SystemVerilog , uvm , Functional Verification , UVM e , UVM-MS , 20nm , Low-Power , Incisive , Mixed-Signal , multi-language , Acellera VIP TSC , mixed signal , MDV , IES , VMM

Digital Design

Five-Minute Tutorial: Multiple View-Only Windows In EDI

Have you ever had a situation where you want to compare two (or more) different areas…

• 1 min read
windows , First Encounter , view-only , viewer , encounter , EDI 10.1 , Digital Implementation , five minute tutorial

Verification

Event Report: Club Formal UK – Cache Coherency, UVM for ABV, and Brainstorming with…

Right before the December holidays it was my privilege to host the first "Club Formal…

• 3 min read
uvm , Vincent Reynolds , ABV , Joerg Mueller , metric driven verification (MDV) , ABVIP , coherency , assertions , Club Formal , UK , MDV , Bob Kurshan , Assertion-based verification

System, PCB, & Package Design 

What's Good About APD’s Die Abstract Libraries? You’ll Need the 16.5 Release to See

In System in Package (SiP) 16.3, the co-design die flow introduced the distributed…

• 10 min read
PCB , IC Packaging and SiP Design , IC Packaging , packaging , PCB design" , Digital SiP design , CML , die abstracts , APD , Allegro 16.5 , IC/package co-design , Allegro Package Designer , Layout , design , "PCB design" , PCB design , die abstract compare , SPB16.5 , Librarians , library , Allegro

System, PCB, & Package Design 

What's Good About Allegro GRE Constraint Region Support? It’s in the 16.5 Release

The 16.5 Global Route Environment ( GRE ) now allows or prohibits tuning in constraint…

• 1 min read
PCB , PCB Layout and routing , constraint region , Routing , Allegro 16.5 , PCB Editor , Layout , "PCB design" , PCB design , SPB16.5 , Allegro PCB Editor , GRE , Allegro

Digital Design

Five-Minute Tutorial: Avoid SI Problems With Better Pin Placement In Encounter Digital…

I know we're over halfway through January already (where does the time go?), but…

• 1 min read
assignPtnPin , SI analysis , noise analysis , encounter , pin placement , EDI 10.1 , Digital Implementation , five minute tutorial

Verification

2012 CES: Top 3 Trends Impacting EDA This Year

For years now consumer electronics have driven (nay, saved) the EDA industry. Hence…

• 4 min read
Intel , DAC , Joe Hupcey III , OLED 3D , TV , Consumer Electronics Show , Formal Analysis , CES , formal , 14nm , EDA360 , CES2012 , OLED , DVcon , apps , ARM , LG

RF Engineering

SpectreRF AppNotes and Tutorials....Still One of our Best Kept Secrets!

Some of you may remember the blog written several years ago " Shhhhh...SpectreRF…

• 3 min read
RF , RF Simulation , analog/RF , APS , HBnoise , envelope , QPSS Analysis , shooting newton , HB , Spectre RF , Spectre AppNotes , MMSIM , pnoise , phase noise , Virtuoso Spectre Simulator GXL , fast envelope , analog , ADE , RF spectre spectreRF , Virtuoso Spectre Simulator XL , Virtuoso , Spectre , RF design , harmonic balance , mixer , VCO , RF Measurement library , pss , SpectreRF tutorials , Oscillator

System, PCB, & Package Design 

What's Good About Allegro PCB Router Inset Vias? See for yourself in 16.5!

Another high density interconnect (HDI) technology that has gained popularity is…

• 1 min read
PCB , PCB Layout and routing , interconnects , inset vias , Routing , layer stacks , High Speed , Allegro 16.5 , PCB Editor , High-Density Interconnect , Layout , via , design , "PCB design" , PCB design , SPB16.5 , Allegro PCB Editor , HDI , Allegro

Verification

Creating the Zynq Virtual Platform, Including Errata

Although I have never contributed any code to the Linux kernel, the headline We are…

• 5 min read
Virtual System Platform , virtual prototoypes , zynq , virtual platforms , IP-XACT , errata , embedded software , SystemC , linux , Embedded Linux , System Design and Verification

Verification

Video: Bob Kurshan, Cadence Fellow and Incisive Formal R&D Leader, talks about Formal…

Continuing the series of introducing you to the people that create the tools you…

• less than a min read
ABV , Formal Analysis , formal , video , Kurshan , cache coherency , IEV , Bob Kurshan , Formal verification , IFV , verification , Assertion-based verification

System, PCB, & Package Design 

What's Good About Allegro Differential Pair Updates? Look to SPB16.5 and See!

The 16.5 Allegro PCB Editor release adds differential pair phase tuning as an alternative…

• 1 min read
PCB , PCB Layout and routing , Allegro 16.5 , PCB Editor , Layout , design , "PCB design" , PCB design , SPB16.5 , Allegro PCB Editor , differential pairs , Differential Pair Support , Allegro

RF Engineering

Nport Application Note has been Updated and Re-Released

Happy New Year! After many requests, I set aside some time and updated the Using…

• less than a min read
nport , RF , RF Simulation , analog/RF , APS , Virtuoso Spectre , HB , Spectre RF , spectre spectreRF , MMSIM , nport settings , RF Block Simulation , analog , Virtuoso Spectre Simulator XL , spectreRF , Spectre , RF design , harmonic balance

Verification

Ubuntu Updates for 2012

I'm overdue to provide an update on how to run Virtual System Platform (VSP) and…

• 6 min read
Virtual System Platform , zynq , GDB , VSP , Incisive , Ubuntu , VirtualBox , SystemC , Virtual Platforms , System Design and Verification

Verification

TLM: The Year in Review, and Trends for 2012

2011 was my first full year in the land of Transaction-Level Modeling (TLM) design…

• 5 min read
High-Level Synthesis , ASIC , TLM , system realization , C-to-Silcon , TSMC , system design , SystemC , Hardware/software co-verification , HLS , C++ , verification
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