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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Breakfast Bytes

October 2017 Breakfast Buffet

https://youtu.be/2HhOBOftlv4 Coming from the roof of Cadence building 10 (camera…

• less than a min read
China , AMD , linley group , semi , cdnlive taiwan , armmobile , pss , microprocessor , portable stimulus

Analog/Custom Design

Simplifying the Memory Design Process

On today’s SOC designs, the memory control logics and memory arrays take up a lot…

• 2 min read
Memory , custom/analog , Spectre , Custom IC Design , Custom IC

Verification

Cadence and Arm Announce Early Access to Xcelium Parallel Logic Simulators on Arm…

On October 24, Cadence and Arm announced early access to the Xcelium Parallel Logic…

• 1 min read
Multi-Core , xcelium , ARM , simulation , announcement

Breakfast Bytes

Andrew Kahng on the Last Semiconductor Scaling Levers

It's going to be academic week here on Breakfast Bytes. There is an anniversary coming…

• 9 min read
scaling , EDA , cloud , andrew kahng , machine learning , moore's law , Breakfast Bytes

Breakfast Bytes

Decoding Formal Club: Arm and Arteris

At the latest meeting of the Decoding Formal Club, organized by Oski and sponsored…

• 8 min read
Jasper User Group , JUG , oski decoding formal club , formal , Oski , Breakfast Bytes , Formal verification

System, PCB, & Package Design 

SI Methodology for Multi-Gigabit Serial Link Interfaces (2 of 8)

Let’s assume that we are working on a PCI Express Gen 4 serial link, running at 16Gbps…

• 3 min read
Serial link analysis , Signal Integrity , Sigrity

Breakfast Bytes

What's For Breakfast? Video Preview October 30th to November 3rd 2017

https://youtu.be/JQVYmENG0gw Coming from the Cadence booth at Arm TechCon …

• less than a min read
ARM Techcon , Rutenbar , Cadence Academic Network , scaling , introduction to vlsi systems , intern , mead and conway , kahng , Kaufman Award , esd alliance

Analog/Custom Design

Virtuosity: Read Mode Done Right

Because of the ease with which you can set up complex sweep, corner and Monte Carlo…

• 4 min read
ADE Explorer , Custom IC Design. Read only , ADE , Analog Design Environment , ADE Assembler

Breakfast Bytes

Why Was Arm Successful in Mobile?

I think that Arm was successful in mobile (and subsequently in other markets) due…

• 5 min read
mobile , Silicon Valley , ARM , Breakfast Bytes

System, PCB, & Package Design 

Signal Integrity Methodology for Multi-Gigabit Serial Link Interfaces (1 of 8)

As data rates for serial link interfaces such as PCI Express® (PCIe®) Gen 4 move…

• 6 min read
Serial link analysis , SI , Multi-Gigabit , IBIS-AMI , PCIe , Signal Integrity , SerDes , Sigrity

The India Circuit

Opportunities in India for IoT

This week we return to the Internet of Things (IoT). My previous blogs on the subject…

• 3 min read
Government of India , CDNLive India , digital india , smart cities , IoT , IT services , Internet of Things

Breakfast Bytes

Mike Muller Gets Emotional at Arm TechCon

As usual, Arm TechCon opened with a keynote by Mike Muller, Arm's CTO. His son is…

• 6 min read
security , IoT , Mike Muller , ARM , Breakfast Bytes , Techcon

System, PCB, & Package Design 

Customer Support Recommends –Team Design in DE-HDL 17.2

Accelerating product time to market, achieving significantly higher productivity…

• 2 min read
PCB , Rapid Adoption Kit , RAK , Support , Team design

Whiteboard Wednesdays

Whiteboard Wednesdays - Automotive Memory Technologies and Trends: Technology Im…

In this week's Whiteboard Wednesdays video, the last of a three part series, Scott…

• less than a min read
Automotive , memory protocols , Whiteboard Wednesdays , Memory , NAND flash , automotive electronics , memory IP , DRAM , memory models

Breakfast Bytes

Xcelium Simulation on Arm Servers

Paul Otellini RIP Paul Otellini was CEO of Intel from 2005-2013. He died in his…

• 4 min read
ARMv8 , Intel , x86 , cloud , mobile , ARM , microprocessor , datacenter , Breakfast Bytes

Analog/Custom Design

The Art of Analog Design Part 6: Response to Frank’s Question to Part 4

In the comments to blog #4, Frank Wiedmann asked about the correlation between the…

• 3 min read
spectre aps , Virtuoso Variation Option , ADE Explorer , mismatch analysis , Analog Simulation , Monte Carlo analysis , DC Mismatch , Custom IC Design

Breakfast Bytes

Putting the Bad Guys in an Arm Lock

This morning Arm announced their Platform Security Architecture (PSA), a new way…

• 6 min read
security , ARM Techcon , mirai , platform security architecture , psa , ARM , Breakfast Bytes , Techcon

Breakfast Bytes

Education, Occupation, and You: Vishal Kapoor at SJSU

Earlier this week, Jim Hogan hosted the next evening at San Jose State University…

• 8 min read
san jose state university , vishal kapoor , san jose state , cognitive science , cognitive era , sjsu , Breakfast Bytes

Breakfast Bytes

What's For Breakfast? Video Preview October 23rd to 27th 2017

https://youtu.be/-9hc6xBOPFw Coming from SJSU Theater (camera Sean) Monday…

• less than a min read
ARM Techcon , formal , Arteris , mobile , ARM , Formal verification
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