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Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Analog/Custom Design

Virtuoso Studio IC23.1 ISR15 Now Available

Virtuoso Studio IC23.1 ISR15 production release is now available for download.

Virtuoso Release Team
• 2 min read
featured , Virtuoso Studio , IC Release , IC Release Blog Announcement , Virtuoso
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Blog - Post List

Latest blogs

Analog/Custom Design

Managing Inherited Connections with CPF in Virtuoso

Let's assume you are managing a schematic-driven top level design in Virtuoso and…

• 4 min read
inherited connections , EDI , Low Power , mixed signal solution , CPF , analog , Mixed-Signal , encounter , Verilog , mixed signal physical implementation open access , Virtuoso , oa , Mixed signal physical implementation , mixed signal , OA: OpenAccess , mixed-signal design , Virtuoso environment , mixed signal implementation , design implementation , Common Power Format

Analog/Custom Design

Things You Didn't Know About Virtuoso: Rapid Adoption Kits

This post isn't directly about tips and tricks for getting the most out of Virtuoso…

• 1 min read
Virtuoso IC6.1.5 , Rapid Adoption Kit , workshop , analog , Constraint-driven , Virtuoso , ViVA , Connectivity-driven , Custom IC Design , RAKs , Virtuoso Layout Suite XL

System, PCB, & Package Design 

What's Good About APD’s Wirebond Color Visibility? You’ll Need the 16.5 Release to…

Prior to the 16.0 release, color and visibility (CV) settings of bond wires in Allegro…

• 2 min read
PCB , PCB Layout and routing , IC Packaging , packaging , visability , APD , Allegro 16.5 , PCB Editor , Allegro Package Designer , advanced package designer , design , PCB design , bond wires , SPB16.5 , color visibility , wirebond color , Allegro

Verification

Tips on Writing Macros in Specman e Language

In this blog, I will present some tips that can be very useful when you write e macros…

• 4 min read
AF , Specman , Functional Verification , Incisive , e language , define-as , writing macros , macros , testbench , simulation , verification

RF Engineering

Measuring 2-Tone Intermodulation Using Envelope-Following Analysis

From time to time, SpectreRF users simulate very large, extracted-view circuits in…

• 4 min read
RF , RF Simulation , analog/RF , envelope , RFIC , HB , Spectre RF , spectre spectreRF , RF designer , Analog Simulation , MMSIM , RF Block Simulation , Virtuoso Spectre Simulator GXL , fast envelope , analog , ADE , RF spectre spectreRF , spectreRF , Spectre , RF design , harmonic balance , SpectreRF tutorials , simulation , wireless integrated circuit verification

Analog/Custom Design

A Quick Tutorial on Managing ECOs Using Pcells in Mixed Signal Designs

The purpose for creating a Pcell is to automate the creation of data. Pcells should…

• 3 min read
ECO , Static timing analysis , EDI , mixed signal design , parasitic , IC 6.1 , mixed signal solution , Open Access , STA , timing model , ECOs , mixed-signal ECOs , Mixed-Signal , encounter , Virtuoso , oa , EDIS , ECOs and PCells , Mixed signal physical implementation , mixed signal , signoff , OpenAccess , Virtuoso environment , mixed signal implementation

Verification

How Debug Breakthroughs are Enabled by In-Circuit Acceleration

We in product management are often accused of jumping the gun and announcing products…

• 5 min read
DAC , CDNLive , Acceleration , debug , Functional Verification , AMD , System Development Suite , Incisive , in-circuit emulation , Palladium XP , Emulation , in-circuit acceleration , Design Automation Conference , DAC breakfast , System Design and Verification

System, PCB, & Package Design 

What's Good About Allegro GRE 2 Point Flow? It’s in the 16.5 Release!

The 16.5 Allegro Global Route Environment (GRE) has been enhanced by what we call…

• 1 min read
PCB , PCB Layout and routing , bundle compression , interconnects , 2 point flow , global route , Routing , High Speed , Allegro 16.5 , PCB Editor , Layout , design , PCB design , SPB16.5 , Allegro PCB Editor , GRE , disabiling bundle compression , Allegro

Verification

The Facts: Why Accelerated VIP Is Needed for SoC Verification

On Tuesday May 15 th Cadence announced the expansion of our VIP Catalog to include…

• 4 min read
AVIP , SystemVerilog , accelerated VIP , Verification IP , uvm , Acceleration , Functional Verification , VIP , Palladium , Palladium XP , Emulation , VIP Catalog , simulation VIP , ACE verification , e language , SCE-MI , SystemC , protocol verification , simulation , verification

Digital Design

Adding Custom Shapes and Text is New and Improved in EDI System 11

You may have noticed that in the Encounter Digital Implementation (EDI) System 11…

• 4 min read
dbGet , add_shape , custom text , custom shapes , add_text , EDI 11.1 , digital implementation , Encounter Digital Implementation , OpenAccess , EDI 11

Verification

American Technology Awards - Finally I Can Explain to my Mom What I am Actually Working…

I think all of us engineers have faced at one point or another the need to explain…

• 2 min read
Rapid Protoytping Platform , Virtual System Platform , virtual platforms , awards , Watson , virtual prototypes , American Technology Awards , Jeopardy , System Development Suite , VSP , Incisive , Palladium XP , Raritan , Mother's Day , System Design and Verification , cloud computing , FPGA-based prototyping

Verification

DAC 2012 Preview: Focus on Formal and ABV Events and Papers

In a few short weeks DAC 2012 will be upon us (June 3-7, 2012 in San Francisco, CA…

• 2 min read
DAC , Incisive Formal Verifier , ABV , Functional Verification , Formal Analysis , formal , "Coverage Unreachability" , coverage unreachability , formal apps , model checking , bypass verification , apps , Lego , User Track , assertions , papers , DAC 2012 , robot , IEV , Design Automation Conference , Rubik's Cube , IFV , Assertion-based verification

Verification

Specman’s Memory Management Orientation Guide (or “Honey – Please Take out the Garbage…

Memory management is not something the Specman user is supposed to worry about. Nobody…

• 9 min read
AF , Specman , Memory , garbage , Functional Verification , garbage collection , Specman garbage collection , Incisive , e language , managing memory , Specman data , memory errors , testbench , simulation , memory management , verification

Verification

Video Tech Tip: Data Path Verification Using a Formal Scoreboard with Incisive Formal…

This 6 minute video is a quick overview of our formal scoreboard app. Specifically…

• less than a min read
scoreboard , ABV , Joerg Mueller , Formal Analysis , formal , video , formal apps , apps , formal scoreboard , IEV , IFV

System, PCB, & Package Design 

What's Good About Allegro PCB Router HDI Capabilities? 16.5 Has a Few New Enhancements

More high-density interconnect (HDI) improvements including the tuning of the auto…

• 1 min read
PCB , PCB Layout and routing , interconnects , inset vias , Routing , via tangency , Allegro 16.5 , via rules , PCB Editor , High-Density Interconnect , Layout , via , via patterns , design , vias , PCB design , SPB16.5 , HDI , microvia , Allegro

System, PCB, & Package Design 

Free PCB Signal Integrity Education from Robert Hanson Continues at Cadence in A…

Over fifty PCB enthusiasts ascended upon the Cadence campus in Austin, Texas last…

• 1 min read
PCB SI , PCB , SI , DDR2 , transmission line , PCB PI , PDN , Austin , Robert Hanson , "PCB SI" , PCB power integrity , Allegro 16.5 , IBIS-AMI , Power Delivery Network , Signal Integrity , PCB Signal integrity , Allegro PCB SI , PCB design , "PCB PI" , PCI Express , "Power Delivery Network" , DDR3 , Allegro

Verification

Xilinx Zynq-7000 Virtual Platform Performance: Native Linux vs. VirtualBox

In my last blog post , I covered three frequently asked questions about using the…

• 5 min read
taskset , virtual platforms , Unity 2D , System Development Suite , embedded software , VSP , Ubuntu , VirtualBox , virtual prototype , Virtual Machine , Linux vs VirtualBox , Unity3D , xilinx , graphics , linux , Zynq-7000 , simulation , ESL , System Design and Verification

Verification

Xilinx Zynq-7000 Virtual Platform Frequently Asked Questions: VirtualBox Edition

The use of virtual machine technology offers great ease of use benefits. Since the…

• 7 min read
VBoxManage , port forwarding , network address translation , eclipse , virtual platforms , NAT , virtual prototypes , embedded software , Xilinx SDK , Ubuntu , VirtualBox , system design , Virtual Machine , FAQ , System Design & Verification , xilinx , Zynq virtual platform , Zynq-7000 , ESL

Digital Design

Five-Minute Tutorial: Understanding the Encounter Power System (EPS) Reports Dir…

No matter how you run your power analysis - with Encounter Power System (EPS) or…

• 3 min read
EDI , rail analysis , EPS reports , tutorial , encounter digital implementation system , EPS , encounter , digital implementation , IRdrop , Power Analysis , powergrid view , EM , five-minute , encounter power system , electromigraion
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