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CadenceLIVE India 2025 Recap – Where Inspiration Meets Innovation

On August 13, 2025, CadenceLIVE India 2025 set the stage for a remarkable convergence…

Reela
• 2 min read
featured , cadence , AI-Driven Design , cadencelive , AI

Analog/Custom Design

Virtuoso Studio IC25.1 ISR1 Now Available

Virtuoso Studio IC25.1 ISR1 production release is now available for download.

Virtuoso Release Team
• 1 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Blog Announcement

Corporate News

MSU Leveraging Intel 16 and the Cadence Tool Flow for Academic Chip Tapeout

Morgan State University (MSU) recently received an Apple Innovation Grant, designed…

Corporate
• 4 min read
news story , featured , Cadence Academic Network

Digital Design

Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML
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Blog - Post List

Latest blogs

Breakfast Bytes

Handling Variability in the Modern Design Cycle

Igor Keller gave an internal presentation on Handling Variability in the Modern Design…

• 6 min read
on chip variation , AOCV , STA , OCV , variability , voltage droop , static timing , layout dependent effects , miller capacitance , SOCV , crosstalk , slew , SSTA

Verification

Preview of an Exciting DVCon

In the overall world of EDA, the Design Automation Conference ( DAC ) is the biggest…

• 3 min read
uvm , prototyping , pswg , Acceleration , Functional Verification , Perspec , System Design and Verification , Palladium , SoC , Emulation , Simulation acceleration , DVcon , Accellera , metric-driven verification , Hardware/software co-verification , portable stimulus , simulation , verification

Breakfast Bytes

What's For Breakfast? Video Preview February 6th to 10th 2017

https://youtu.be/XOS4sfILahc Coming from Design Con 2017 Monday: He Who…

• less than a min read
security , Automotive , Routing , TSMC , business strategy , Innovus , privacy

Verification

IEEE Std 1647™ 2016 - e Language - New Standard Publication

Congratulations to the IEEE-1647 e Functional Verification Language Working Group…

• 2 min read
IEEE 1647 , Specman , e , e language , specman elite

Breakfast Bytes

The ASML Standard Node

One of the first posts I wrote here at Breakfast Bytes was Where Does 5 Really Mean…

• 3 min read
mmhp , cphp , standard node , EUV

Breakfast Bytes

The Book for Practicing Formal Verification Engineers

At the no-longer-so-recent Jasper User Group JUG last year, the keynote was by Erik…

• 3 min read
formal verification book , Formal verification

Whiteboard Wednesdays

Whiteboard Wednesdays - Evolution of Ethernet: Not Your Grandfather's Ethernet

In this week's Whiteboard Wednesdays, Scott Jacobson wraps up his three-part series…

• less than a min read
Verification IP , Whiteboard Wednesdays , VIP , Automotive Ethernet , Ethernet

Breakfast Bytes

ENIAC, EDSAC and Colossus... and the Difference Engine

There are lots of claims to be the first computer, depending on your definition of…

• 5 min read
edsac , analytical engine , mercury delay line , difference engine , first stored program computer , eniac

Analog/Custom Design

Virtuoso Video Diary: Is It That Easy to Edit in the Virtuoso Schematic Editor?

Creating a neat and organized schematic is extremely important, and often requires…

• 3 min read
Virtuoso Schematic Editor , VSE L , Advanced Node , VSE XL , Virtuoso Video Diary , Custom IC Design

Breakfast Bytes

Andrzej Strojwas Receives the 2016 Kaufman Award

Last night was the annual Kaufman Award dinner to present the award to this year…

• 6 min read
Kaufman Award , kaufman award dinner , andrzej strojwas , pdf solutions

Breakfast Bytes

What's For Breakfast? Video Preview January 30th to February 3rd 2017

https://youtu.be/NxgrCMJYRew Coming from Kaufman Award Dinner Monday: The…

• less than a min read
asml standard node , formal , Kaufman Award , STA , andrzej strojwas , variability , standard node , Formal verification

Breakfast Bytes

SPIE Advanced Lithography Conference

SPIE is the international society for optics and photonics, with the purpose of …

• 4 min read
lithography , imec.spie advanced lithography , SPIE

Breakfast Bytes

Frank Chen of a16z on 16 Things About Autonomous Vehicles

In a recent a16z presentation, Frank Chen, a partner at Andreessen-Horowitz, says…

• 6 min read
autonomous cars , self-driving cars , a16z , autonomous vehicles

Breakfast Bytes

ENNS 2017: Deep Learning, the New Moore's Law

One of the hottest areas in systems right now is deep learning: neural networks,…

• 3 min read
CVPR , deep learning , enns 2017 , CNN

Whiteboard Wednesdays

Whiteboard Wednesdays - Evolution of Ethernet: The Early Days

In this week's Whiteboard Wednesdays video, the second in a three-part series, Scott…

• less than a min read
Verification IP , Whiteboard Wednesdays , Scott Jacobson , VIP , Ethernet

Analog/Custom Design

New Virtuoso ADE Suite Wins Product of the Year

Cadence today announced that its next-generation Virtuoso® Analog Design Environment…

• 1 min read
ade suite , electronic products , product of the year

Breakfast Bytes

Nibbles: Breakfast Bytes Predictions 2017

It's that time of year when pundits try and predict major changes that will happen…

• 3 min read
2016 predictions , 2017 predictions

Verification

Bare Metal Tests and Hardware-Software Co-Verification

One interesting question that arises from time to time is whether the Cadence® Perspec…

• 4 min read
hardware-software co-verification , uvm , pswg , Acceleration , Perspec , virtual platform , System Design and Verification , Emulation , System simulation and analysis , Accellera , FPGA prototypes , testbench , portable stimulus , silicon , bare metal , verification

Breakfast Bytes

RISC-V "The thing that you learn and the thing that you use are the same"

The Electronic System Design Alliance (fka EDAC) has been organizing evening meetings…

• 7 min read
risc-v , cadence , isa , Jim Hogan , instruction set architecture , sifive , esd alliance
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