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Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
• 8 min read
featured , physical ai , HGR , AI , Honda

Corporate News

The New ASK Portal Brings a Smarter, Faster, and More Intuitive Experience

Finding the right support content should be simple, fast, and intuitive. The new…

Corporate
• 2 min read
featured , customer support , New ASK Portal , ASK Gen AI
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Blog - Post List
Latest blogs

Analog/Custom Design

SKILL for the Skilled: Virtuoso Applications of SKILL++

In this posting, I continue looking at applications of SKILL++. In particular, I…

• 4 min read
Team SKILL , Virtuoso IC6.1.5 , closures , IC 6.1.5 , sort , Virtuoso , Lisp , Custom IC Design , SKILL++ , sorting , SKILL

Verification

OVM 2.1.2 -- Getting You Ready for UVM

Talk about stability -- OVM 2.1.1 has had 18 months as the core of Accellera's UVM…

• 1 min read
SystemVerilog , DAC , uvm , OVM , Incisive , OVM SV , Funcional Verification , Accellera VIP TSC , IES , OVMWorld , OVM 2.1

System, PCB, & Package Design 

What's Good About Allegro Embedded Components? SPB16.5 Has Many New Enhancements

The Allegro 16.5 release was made available on May 17, 2011! This release adds additional…

• 5 min read
PCB , PCB Layout and routing , IC Packaging and SiP Design , Constraint-driven PCB Design flow , embedded components , DDR3 SoC Realization , IC Packaging , PDN , EDA360 , High Speed , Allegro Design Workbench , Library flow , Allegro 16.5 , Library and design data management , Power Delivery Network , PCB Editor , Design Entry HDL , Layout , design data management , design , miniaturization , PCB design , SPB16.5 , Allegro PCB Editor , Librarians , library , PCB Capture , DDR3 , Allegro

Digital Design

Five-Minute Tutorial: Avoiding The Use Of FILL1 Cells

A new thing that we're seeing with some 45nm libraries is the rule that single-wide…

• 2 min read
EDI , fill1 , filler cells , encounter , 45nm , checkFiller , Digital Implementation , Placement

System, PCB, & Package Design 

Miniaturization Through Embedding Packaged Components – Part2

This blog was written by a guest blogger – Mark Beesley of AT&S. His company is…

• 2 min read
embedded components , AT&S , embedded die in laminate , ECP , TeamAllegro , PCB Editor , miniaturization , Beesley , "PCB design" , SPB16.5 , Allegro PCB Editor , microvia , Allegro

Verification

Pre-RTL Software Development -- You Can't Get Your Product to Market Without It!

It's been an exciting month for the System Realization team with the announcement…

• 2 min read
Virtual System Platform , TLM 2.0 , virtual prototype

Verification

Blazing a Trail With Ubuntu

One of the most popular blogs I wrote is running Incisive on Ubuntu . I have had…

• 3 min read
SystemC debugging , Virtual System Platform , debug , Ubuntu , SystemC , debugging , linux , System Design and Verification

Analog/Custom Design

CPF Low Power Simulation with Analog and Mixed-Signal Design (CPF-AMS)

We have been talking about low power simulation and the Common Power Format (CPF…

• 2 min read
Low Power , CPF , Verilog-AMS , analog , Mixed-Signal , Spectre , Connect Module , mixed signal , wreal , SPICE

Verification

A Look at the Ongoing Functional Verification Seminar Series

Being a Marketing guy, one thing that I really enjoy is getting on the road for…

• 2 min read
Functional Verification , formal , Incisive , Mixed-Signal , metric-driven verification , MDV , IEV , IFV

Digital Design

Tab Completion with Encounter's dbGet Command: Smarter Than You Might Think

If there's one thing that makes navigating a UNIX command line or tool console more…

• 1 min read
dbGet , tab completion , screencast , encounter , Digital Implementation , Encounter Digital Implementation

Digital Design

Five-Minute Tutorial: Fixing SI Victim Nets

It's hard to believe there was a time when we didn't even run signal integrity analysis…

• 2 min read
SI , EDI , SI victim nets , SI analysis , NanoRoute , encounter , victim nets , Signal Integrity , Digital Implementation , five minute

System, PCB, & Package Design 

Cadence OrCAD Capture Marketplace -- The Cool Factors

Hey, did you hear about the new Cadence OrCAD Capture Marketplace? It has the first…

• 2 min read
PCB , Marketplace , on-line store , OrCAD Capture Marketplace , applications , Capture CIS , OrCAD online store , Team OrCAD , OrCAD , apps

Verification

Panel Discussion: Applying High-Level Synthesis in an SoC Flow

Last Thursday, EETimes hosted a virtual System on Chip event focused on IP integration…

• 6 min read
IP , system on chip , BDTI , SoC , EETimes , Tensilica , Bluespec , SystemC , Synthesis , high level synthesis , HLS , C++ , ESL , System Design and Verification

Verification

Sometimes the Real World Needs Assertions Too

Every once in a while, I like to do a lightweight blog post linking my work world…

• 3 min read
ABV , asssertion-based verification , Functional Verification , formal , assertions

Verification

2011 CDNLive EMEA Highlights and Image Gallery: An EDA360 Spring Festival of Del…

Last week teammate Adam Sherer and I had the honor of representing the Incisive functional…

• 3 min read
RPP , Joe Hupcey III , Specman , Virtual System Platform , AVS , CDNLive , Functional Verification , Adaptive Voltage Scaling , Palladium , System Development Suite , EDA360 , VSP , Incisive , festival , Adam Sherer , Palladium XP , Philippe Magarshack , EMEA , Rapid Prototyping Platform , IEV , Incisive Enterprise Simulator (IES) , IES , Techcon , stmicroelectronics , IES-XL

Digital Design

Five-Minute Tutorial: Setting Up Clock Routing Rules

Hi, and welcome back to another Five-Minute Tutorial! Yes, I know it's been a while…

• 3 min read
EDI , clock routing , Routing , tutorial , encounter , Shielding , clocks , .ctstch , Digital Implementation , five-minute

System, PCB, & Package Design 

Miniaturization Through Embedded Packaged Components

As consumers we are very familiar with product miniaturization trends. We demand…

• 2 min read
PCB , PCB Layout and routing , IC Packaging and SiP Design , embedded components , PCB PI , IC Packaging , PDN , PCB Signal and power integrity , Power Integrity , PCB power integrity , Allegro 16.5 , TeamAllegro , High-Density Interconnect , miniaturization , PCB design , SPB16.5 , Allegro PCB Editor , HDI , Allegro

Verification

Free Webinar This Thursday: Rapid Design Bring-Up Using Formal and Simulation To…

Allow us to shamelessly promote a free webinar (including a live demo) this Thursday…

• 2 min read
Joe Hupcey III , ABV , CDNLive , Functional Verification , Metric Driven Verification , Formal Analysis , formal , webinar , SVA , Chris Komar , Silicon Realization , PSL , coverage driven verification (CDV) , assertions , MDV , IEV , Formal verification , Assertion-based verification

Verification

System Development Suite - Connecting Software to Hardware Design and Verificati…

I've been at CDNLive! EMEA watching demos of the newly announced System Development…

• 2 min read
ECO , Virtual System Platform , TLM , hardware , System Design and Verification , C-to-Silcon , System Development Suite , software , SystemC , verification
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