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The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
• 8 min read
featured , physical ai , HGR , AI , Honda
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Blog - Post List
Latest blogs

Verification

Join Us at FMCAD October 20-23

Are you deeply interested in formal and assertion-based verification technology?…

• less than a min read
Alok Jain , ABV , Functional Verification , Formal Analysis , formal , FMCAD , IEV , IFV

System, PCB, & Package Design 

What's Good About AMS Simulator New Design Templates? They’re in the SPB16.3 Release

What's Good About AMS Simulator New Design Templates? They're in the SPB16.3 Release…

• 1 min read
SPB16.3 , AMS , AMS simulator , SPB 16.3 , PSPICE , AMS simulation , Design Entry , Schematic

Verification

All I Really Need to Know About MDV I Learned From Hollywood - Part 2

My last blog entry began a series using quotes from Hollywood movies to illustrate…

• 2 min read
vPlan , verification planning , Verification IP modeling , metric-driven verification , MDV

SoC and IP

HP’s memristor finds a commercial semiconductor vendor: Hynix

The rumor at the recent Flash Memory Summit held earlier this month was that HP was…

• less than a min read

SoC and IP

Toshiba 24nm, 64-Gbit NAND Flash: Just a silly nanometer shorter

Toshiba announced today that it has initiated mass production of NAND Flash memories…

• less than a min read

SoC and IP

17 SSDs reviewed by Tom’s Hardware

We’re still at the stage where there can be appreciable differences in the performance…

• 1 min read

SoC and IP

Huawei talks Smart Memory at Hot Chips 22: “The only practical solution”

Last week saw the 22nd Hot Chips conference, held at held Stanford University, and…

• 3 min read

SoC and IP

A non-exhaustive list of 150 SSD vendors

A recent check of the Yahoo! Finance boards showed some skepticism about my previous…

• 1 min read

SoC and IP

PCM (now with carbon nanotubes!) programming current drops two orders of magnitu…

A fascinating Masters thesis written by Feng Xiong details the fabrication and testing…

• 1 min read

SoC and IP

Seagate and Samsung to jointly develop enterprise-class SSD controller -- a little…

A bit more than a week ago, HDD leader Seagate and NAND Flash leader Samsung jointly…

• 1 min read

Verification

All I Really Need to Know About MDV I Learned From Hollywood - Part 1

True story: this series of blog posts is inspired by a dream. I recently gave a presentation…

• 3 min read
vPlan , verification planning , Verification IP modeling , metric-driven verification , MDV

SoC and IP

8 key takeaways for system design teams from the Flash Memory Summit

Cadence’s Senior Manager of Technical Communications and a longtime EDA observer…

• less than a min read

Analog/Custom Design

Things You Didn't Know About Virtuoso: Outputs Setup in ADE XL

Continuing on our exploration of ADE XL (see here and here for previous articles…

• 5 min read
IC 6.1 , Analog Simulation , analog , ADE , Virtuoso IC 6.1.3 , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , ADE-XL , IC 6.1.4 , Custom IC Design

System, PCB, & Package Design 

What's Good About Capture Objects Look and Feel? You Can Change Them in SPB16.3!

The SPB16.3 release of Allegro Design Entry CIS (known as Capture) has some cool…

• 2 min read
"capture CIS" , SPB16.3 , Allegro Design Entry , Capture CIS' , Design Entry CIS , OrCAD Capture , Allegro 16.3 , SPB 16.3 , Capture CIS , Capture-CIS , SPB , design , Design Entry , PCB Capture , Schematic

SoC and IP

Kingston DDR3 RAM cracks 3Gtransfers/sec barrier, achieves 3.068 Gtransfers/sec amid…

Mix liquid nitrogen and Kingston’s HyperX DDR3-2333 SDRAM modules and you get 3068…

• 1 min read

Digital Design

CDNLive! Silicon Valley Abstract Deadline Extended 1 Week

The deadline for submitting abstracts to CDNLive! Silicion Valley 2010 has been extended…

• less than a min read
CDNLive!

Verification

System Realization Webinars Start Sept 8th

Starting September 8th Cadence will be hosting a series of webinars about various…

• 2 min read
TLM , webinars , system realization , Calypto , Imperas , CircuitSutra , XtremeEDA , ESL

SoC and IP

OCZ accentuates the positive (SSDs) and eliminates the negative (low-margin DRAM…

PC add-on vendor OCZ has announced today that its future is in SSDs and high-speed…

• 1 min read

Verification

Performance Tips and Tricks: Another Specman Performance Series

Building on the great success of Efrat Shneydor's previous blog series, Performance…

• 1 min read
performance , Specman , Functional Verification , Testbench simulation , EDA , e , team specman , Aspect Oriented Programming , AOP
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