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Corporate News

The Three-Layer Cake: The Foundation Behind Intelligent Engineering

Artificial intelligence is rapidly becoming the engine behind the next era of technology…

Corporate
• 7 min read
featured , infrastructure ai , agentic ai , Principled Simulation , physical ai

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe

Corporate News

Honda + Cadence = Physical AI (part 1): What Does “Physical AI” Really Mean?

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The more widely the term …

Corporate
• 7 min read
featured , physical ai , HGR , AI , Honda

Corporate News

Design for AI and AI for Design

The semiconductor industry is experiencing a once-in-a-generation transformation…

Corporate
• 6 min read
Allegro X AI , featured , infrastructure ai , agentic ai , Integrity 3D-IC Platform
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Blog - Post List
Latest blogs

SoC and IP

Cadence PCIe Solutions: Configurable, Compliant, and Low Power

Cadence was the first IP provider to bring PCIe Gen3 Controllers to the market. Since…

• 1 min read
PCIe controller , PCIe IP , PCIe low power , PCIe , PCIe PHY

Verification

Incisive Simulation and Verification: Top 10 New Things I Learned While Browsing…

Cadence Online Support, https://support.cadence.com/ , provides access to support…

• 5 min read
COS , IMC , SystemVerilog , random stability , LPS , UVM-ML , CPF , debugging tips , Cadence Online Support , UVM ML , troubleshooting , irun , IES , vManager

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Multiple Constraint Region Assignments? 16.6…

Just a short post today. In the 16.6 Allegro PCB Editor release, multiple region…

• less than a min read
constraint region , Allegro 16.6 , SPB , PCB Editor , BGA , Layout

Whiteboard Wednesdays

Whiteboard Wednesdays - Get to Know 802.11a/c Wireless Analog Front End Solution

In this week's Whiteboard Wednesdays, Priyank Shukla discusses Cadence's wireless…

• less than a min read
Whiteboard Wednesdays , wireless AFE , 802.11a/c , analog front end , AFE

SoC and IP

Ethernet in Cars - The Next Big Thing for Ethernet

Ethernet is coming to cars. Cars now have rear-view cameras and infotainment systems…

• 2 min read
CDNLive , Automotive Ethernet , automotive electronics , broadcom , Ethernet , Ethernet PHYs

Whiteboard Wednesdays

Whiteboard Wednesdays - See How Customizable Processors Can Help to Offload Your…

In this week's Whiteboard Wednesdays, we take a little different approach and show…

• less than a min read
Whiteboard Wednesdays , IP , customizable processors , Tensilica , offload application processor

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Dual-Side Contact Components? It’s in the 16…

The use of dual-sided contact components when placed on internal layers of the PCB…

• 3 min read
PCB Layout and routing , Allegro GUI , inset vias , Allegro 16.6 , Routing , staggered vias , layer stacks , SPB , PCB Editor , PCB routing , Layout , via , PCB design , Allegro PCB Editor , buried vias , HDI , PCB Capture

Analog/Custom Design

EDA Plus Academia: A Perfect Game, Set and Match

Excuse the tennis analogy, but just coming out of Wimbledon! However, EDA and academia…

• 2 min read
DAC , Carnegie Mellon University , EDA , memory circuit yield , Semiconductor , university program

Whiteboard Wednesdays

Whiteboard Wednesdays - Verifying Solid State Drives Incorporating NVM Express

In this week's Whiteboard Wednesdays, Mukul Dawar explains the NVM Express protocol…

• less than a min read
Verification IP , Whiteboard Wednesdays , Functional Verification , verifiying SSDs , verifying solid state drives , NVM Express protocol

Analog/Custom Design

Virtuosity: 21 Things I Learned in May and June 2014 by Browsing Cadence Online …

Application Notes 1. Setting PVS to QRC av_extracted Flow with tsmc28 (& tsmc40…

• 4 min read
Variability Aware Design , ADE GXL , VSR , Routing , ADE XL , Layout , Spectre , Analog Design Environment , Placement , Virtuoso Layout Suite XL , IC 6.1.6

Verification

Implementing User-Defined Register Access Policies with vr_ad and IPXACT

The register and memory package vr_ad for Specman is used in pretty much every verification…

• 2 min read
AF , Specman , debug , vr_ad , e code , Funcional Verification , Incisive Enterprise Simulator (IES) , ipxact

Whiteboard Wednesdays

Whiteboard Wednesdays - Leading Up to PCI Express 4.0

In this week's Whiteboard Wednesdays, Moshik Rubin discusses the history of the PCI…

• less than a min read
Whiteboard Wednesdays , IP , PCIe Gen4 , PCI Express

System, PCB, & Package Design 

What's Good About Allegro PCB Editor Design Partitioning? 16.6 Has Several New Enhancements

The 16.6 release of Allegro PCB Editor has several new enhancements for team design…

• 3 min read
Allegro 16.6 , 16.6 , Team design , SPB , PCB Editor , Constraint Manager , Allegro PCB Editor

Whiteboard Wednesdays

Whiteboard Wednesdays - Using USB IP Controllers in Today's Devices

In this week's Whiteboard Wednesdays, Jacek Duda follows up on his earlier video…

• less than a min read
USB IP controllers , Whiteboard Wednesdays , USB controllers

Whiteboard Wednesdays

Whiteboard Wednesdays—Improving Power Optimization with PCI Express

In this week's Whiteboard Wednesdays video, Arif Khan takes a closer look at PCI…

• less than a min read
Whiteboard Wednesdays , PCIe , PCI Express , power optimization

System, PCB, & Package Design 

What's Good About Allegro PCB Editor IPC 2581 Data Transfer Standard? 16.6 Has It

The 16.6 Allegro PCB Editor now has IPC 2581 data transfer capabilities. Thanks to…

• 10 min read
PCB , PCB Layout and routing , Cadence Design Systems , Allegro GUI , Allegro 16.6 , cadence , 16.6 , layer stacks , artwork , SPB , interfaces , PCB Editor , Layout , design , PCB design , Grzenia , Allegro PCB Editor , Standards based Interfaces , Allegro

Whiteboard Wednesdays

Whiteboard Wednesdays - Improving Hardware Verification with Accelerated Verification…

In this week's Whiteboard Wednesdays, Tom Hackett talks about Accelerated Verification…

• less than a min read
AVIP , accelerated VIP , Verification IP , Whiteboard Wednesdays , VIP , hardware verification

System, PCB, & Package Design 

Build Components Quickly and Easily with Pre-Defined Escape Routing Using Cadence…

When it comes to designing a dense flip-chip die - or even defining a BGA for a complex…

• 5 min read
Allegro package design , reusable tiles , EDA , package design , SiP Layout , substrate design tools

RF Engineering

Distortion Summary in New CDNLive YouTube Video and at IEEE IMS2014 Next Week!

Hi Folks, Check out this great new video on YouTube: CDNLive SV 2014: PMC Improves…

• less than a min read
Wilsey , Spectre RF , spectreRF , RF design , harmonic balance , Distortion
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