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Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
• 8 min read
featured , physical ai , HGR , AI , Honda

Corporate News

The New ASK Portal Brings a Smarter, Faster, and More Intuitive Experience

Finding the right support content should be simple, fast, and intuitive. The new…

Corporate
• 2 min read
featured , customer support , New ASK Portal , ASK Gen AI

Corporate News

The Three-Layer Cake: The Foundation Behind Intelligent Engineering

Artificial intelligence is rapidly becoming the engine behind the next era of technology…

Corporate
• 7 min read
featured , infrastructure ai , agentic ai , Principled Simulation , physical ai

Data Center

Cadence Accelerates Digital Twin–Driven Data Center AI Modernization with HPE

Solution will maximize data center and AI factory profitability while delivering…

Corporate
• 3 min read
news story , featured , infrastructure ai , data center , hpe
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

Evolution and Synthesis

If you have not yet seen it, Jim Hogan and Paul McLellan wrote a great piece over…

• 2 min read
High-Level Synthesis , RTL , Hogan , EETimes , SystemC , evolution , HLS , McLellan

Analog/Custom Design

Video Demo -- Increase Simulation Accuracy and Efficiency With SpectreMDL

MDL is an immensely powerful feature in our simulators that allows designers to run…

• less than a min read

Analog/Custom Design

Video Demo -- Increase Simulation Accuracy and Efficiency With SpectreMDL

Measurement Description Language (MDL) is an immensely powerful feature in our simulators…

• less than a min read
analog , Virtuoso , spectreMDL , Spectre , MDL , Custom IC Design

System, PCB, & Package Design 

What's Good About Part Developer and Fonts? You Can Change Them in SPB16.3!

PCB Librarian Expert (sometimes known as Part Developer or PDV ) is the librarian…

• 2 min read
SPB16.3 , part developer , PDV Symbol , Allegro 16.3 , SPB 16.3 , SPB , design , fonts , Design Entry , Librarians , ConceptHDL , library , Allegro

Verification

Does It Get Any Better than CDNLive! India?

I've just returned from CDNLive! India in Bangalore, fired up with the huge crowd…

• 3 min read
CDNLive , formal , OVM , ISX , MDV , IFV , techtorial , India , verification

System, PCB, & Package Design 

A Shorter, Predictable Design Cycle for Complex PCBs - Dynamic Phase Control

This is second in a series of blog posts about making your design cycles shorter…

• 1 min read
PCB , PCB Layout and routing , DDR2 , ECSets , Constraint-driven PCB Design flow , Allegro 16.3 , phase control , XAUI , PCB design , dynamic phase control , DDR3 , Allegro

System, PCB, & Package Design 

What's Good About PCB SI Case Management? SPB16.3 Has a Few New Enhancements!

The SPB16.3 PCB SI release has simplified the use of case management. In previous…

• 1 min read
PCB SI , PCB , SI , RF , SPB16.3 , SiP , Signal Intregrity , SigXP UI , Allegro 16.3 , SPB 16.3 , SPB , PCB design

Verification

“Formal Design” or “Formal Verification”-- What is the Right Label?

Shortly after DAC 2010, Gabe Morretti wrote a couple of interesting blogs (reference…

• 3 min read
DAC , uvm , ABV , CDNLive , Functional Verification , formal , OVM , EDA360 , EDA , SoC , Silicon Realization , SoC Connectivity , connectivity , IFV

Verification

Broadcom Presentation Shows Value of Transaction-Based Acceleration

Wow - what a paper! At CDNLive! Silicon Valley 2010 , the joint paper from Broadcom…

• 1 min read
CDNLive , Acceleration , System Design and Verification , Palladium , broadcom , Emulation , transaction-based , simulation , verification

RF Engineering

New Fast Envelope in MMSIM10.1 is *Really* Fast and Accurate!

Traditionally, envelope analysis is used to simulate circuits with modulated inputs…

• 1 min read
RF , envelope , MMSIM , fast envelope , simulation

Verification

Open Mobile Summit -- What‘s Happening in the World of Applications

I attended last week's Open Mobile Summit in San Francisco last week. This is a twice…

• 4 min read
Open Mobile Summit , applications , android , EDA360 , google , apps , superphones , smartphones

System, PCB, & Package Design 

What's Good About Allegro GRE Planning? You’ll Need the SPB16.3 Release to See!

This new SPB16.3 Global Route Environment (GRE) Plan Status and Router Status functionality…

• 2 min read
PCB , PCB Layout and routing , SPB16.3 , global route , Routing , Allegro 16.3 , SPB 16.3 , SPB , PCB Editor , Layout , PCB design , Allegro PCB Editor , GRE , Predictable PCB design , Allegro

Verification

System Bring-Up - THE Critical Path in the System Development Process

The electronic industry is moving from hardware-defined products to software-defined…

• 2 min read
prototyping , Bring-up , Acceleration , debug , system realization , Palladium , Emulation , bringup , System Design and Verification , verification

Verification

2010 CDNLive Silicon Valley Photo Blog: Silicon Realization, ABV, OVM, MDV, Specman…

If you are running short on time and can't view all the videos of the 2010 CDNLive…

• less than a min read
SystemVerilog , Cadence Connections , NextOp , AMS , uvm , Specman , ABV , Zocalo , verification strategy , CDNLive , Functional Verification , Formal Analysis , formal , OVM , EDA360 , Mixed Signal Verification , e , SoC , SVA , ISX (Incisive Software Extensions) , Silicon Realization , AMIQ , assertion synthesis , Aspect Oriented Programming , ISX , MDV , IEV , IFV , AOP

Verification

The Amazing Diversity of the SoC Conference

Although I attend a number of conferences and tradeshows each year, most of these…

• 3 min read
SOC Conference , uvm , Multi-Core , SoC , multicore , yield , verification

System, PCB, & Package Design 

Favorite Features of an IC Package Designer: Wirebonding

This is the fourth in a series of discussions we would like to open up regarding…

• 1 min read
SPB16.3 , package , IC Package , Digital SiP design , 3D-IC , Allegro 16.3 , IC Packaging and SiP , APD , wirebonds , IC Packaging & SiP design , SPB , wirebonding , Physical layout and co-design , Kulicke & Soffa

Analog/Custom Design

SKILL for the Skilled: Making Programs Clear and Concise

The SKILL programming language augments Cadence core tool functionality for Virtuoso…

• 3 min read
Team SKILL , programming , analog , Virtuoso , Custom IC Design , SKILL , Allegro

SoC and IP

STT-MRAM -- from Seagate???

On June 12, 1989, I flew to Minnesota from Denver, Colorado, picked up a rental car…

• 2 min read

Digital Design

CDNLive! Silicon Valley 2010: User Papers Explore Digital Implementation

I previously wrote about the general session of the 2010 CDNLive! Silicon Valley…

• 2 min read
EDA360 , Silicon Realization , Digital Implementation , CDNLive!
CDNS - Fix Layout Hompage