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The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Corporate News

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate
• 8 min read
featured , physical ai , HGR , AI , Honda
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Blog - Post List
Latest blogs

Analog/Custom Design

Part 1 - Constraint-driven Physical Design Speeds Custom IC Design Convergence

In this introductory Part I of V of this blog I will discuss the advanced node design…

• 1 min read
Virtuoso Space-based Router , VSR , IC 6.1 , CMP , chip optimizer , Litho , DFY , CAA , Constraint-driven , Virtuoso IC 6.1.3 , Connectivity-driven , IC 6.1.4 , Custom IC Design , space based router , DFM

Verification

Industry Discussion about High Level Synthesis

Many of you know that Richard Goering has joined Cadence and now writes a blog called…

• less than a min read
High-Level Synthesis , CTOS , TLM , System Design and Verification , Richard Goering , incisive c-to-silicon

Verification

Survey Results For "Booth-Centric" vs. "Paper Centric" Shows

In my last post I shared how my annual tour of the tour of the ESC show floor inspired…

• 2 min read
events , DAC , Specman , CDNLive , Functional Verification , CDNLive San Jose 2008 , ESC , DVcon , Xuropa

Digital Design

Noise Induced Double Clocking Explained

In my previous blog on noise analysis accuracy , I mentioned something called “double…

• 1 min read
CadMOS , encounter , Digital Implementation , double clocking , Enouter Timing System , CeltIC

Analog/Custom Design

IC Design vs. Manufacturing Objectives - Can Both Be Achieved Concurrently?

IC designers and foundries typically have different objectives. IC designers want…

• 3 min read
Chip finishing , Virtuoso Space-based Router , Physical placement and layout , Virtuoso IC 6.1.3 , IC 6.1.4 , Custom IC Design , custom design technology

Verification

Performance-Aware e Coding Guidelines – Part 3

The constraint solver is a powerful and fun to use tool. Actually, it is so much…

• 1 min read
performance , Specman , Functional Verification , tech tips , e , specman elite , Incisive Enterprise Simulator (IES) , IES , IES-XL

Digital Design

Constraint Construction: What's Its Function? Part 4 of 4

This is the last in the series of Constraint Construction blogs ! Today we're going…

• 2 min read
design rules , encounter , rtl compiler , Digital Implementation , modes of operation

System, PCB, & Package Design 

What's Good About DEHDL-CM Physical and Spacing Constraints? You'll need SPB16.2

That's right - the SPB16.2 release now includes support for Physical and Spacing…

• 2 min read
16.01 , SPB 16.2 , DEHDL , Design Entry HDL , PCB design , Allegro

Verification

Homeschoolers Hungry for Technology

Over the weekend I attended the 2009 Minnesota Homeschool Conference in downtown…

• 4 min read
System Design and Verification , Lego , mindstorms NXT

Digital Design

Encounter Digital Implementation System 8.1 San Jose Live Blog

I'll be live blogging from the Cadence Campus in San Jose today. We're doing a seminar…

• less than a min read
Low Power , encounter , Digital Implementation , mixed signal , design closure , Encounter Digital Implementation System 8.1

Verification

Tracing TLM 2.0 Activity in an ESL Design – Part 2

In my last post I discussed two ad hoc approaches for tracing TLM 2.0 activity in…

• 4 min read
System Design and Verification , TLM 2.0 , George Frazier , SystemC , TLM 2.0 Trace

Verification

Another New Blog About the e Language

We are compelled to briefly interrupt Efrat's excellent series on Performance-Aware…

• less than a min read
IEEE 1647 , Specman , Functional Verification , e , OVMWorld

Verification

Verification of AUTOSAR Software Using a SystemC Virtual Platform

[Please welcome ISX R&D team member Markus Winterholer back to the Team ESL blog…

• 2 min read
AUTOSAR , BSW , System Design and Verification , RTE , SystemC , VFB , ISX

Verification

ESC and "Booth-Centric" vs. "Paper Centric" Shows

Last Wednesday I walked the floor of the Embedded Systems Conference (ESC) , with…

• 2 min read
events , DAC , CDNLive , Functional Verification , ESC , DVcon

Verification

Performance-Aware e Coding Guidelines – Part 2

Building on Part 1 where I talked about the “do’s and don’ts” of List performance…

• 2 min read
performance , IntelliGen , Specman , Functional Verification , tech tips , OVM e , e , OVM-e , specman elite , Incisive Enterprise Simulator (IES) , IES , AOP , IES-XL

Analog/Custom Design

Virtuoso, the SATs, and the Dark Knight - Part II

Well, are you still wondering what Virtuoso has to do with the SATs and The Dark…

• 3 min read
Virtuoso IC 6.1.3 , Virtuoso , Custom IC Design

Verification

Observations From the Embedded Systems Conference

Yes, there was another Embedded Systems Conference this year. Several "multi-year…

• 2 min read
Embedded Systems Conference , RTL , System Design and Verification , ESL

Verification

EDN's 19th Annual Innovation Awards

Two of Cadence system D&V products have been selected as the finalists for the EDN…

• 1 min read
System Design and Verification , Palladium , EDN , dpa , C-to-Silicon Compiler

Verification

C-to-Silicon Compiler: A High Level and a Low Level Synthesis Tool

Some customers have inquired if C-to-Silicon Compiler (CtoS) is a “Low Level” Synthesis…

• 1 min read
High-Level Synthesis , CTOS , TLM , high-level synthesis adoption , RTL , System Design and Verification , TLM 2.0 , C-to-Silicon , SystemC , C-to-Silicon Compiler , ESL , architect
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