Cadence Blogs

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate 25 Jun 2026 • 6 min read

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate 24 Jun 2026 • 2 min read

featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate 23 Jun 2026 • 3 min read

drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA

Honda + Cadence = Physical AI (part 2): Where Physical AI Will Be Won

Hello everyone, I'm Atsushi Ogawa, Center Head of HGR. The real challenge of physical…

Corporate 22 Jun 2026 • 8 min read

featured , physical ai , HGR , AI , Honda

cdns - all_blogs_categories

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Learning and Support 63
RF Engineering 116
SoC and IP 435
System, PCB, & Package Design 1016
Verification 1326
Cadence Japan 18
Physical Systems Simulation 24

CFD（数値流体力学) 45
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カスタムIC／ミックスシグナル 199
PCB、IC封装：设计与仿真分析 136
PCB解析／ICパッケージ解析 44
PCB設計／ICパッケージ設計 61
RF /マイクロ波設計 45
Spotlight Taiwan 64
The India Circuit 93
定制IC芯片设计 79
データセンター 7

Whiteboard Wednesdays 253

Blog - Post List

Latest blogs

What's Good About a Table of Contents Generator? - Download SPB16.2 and See!

It's here! It's really here!!! I've spoken with many customers over the past several…

Jerry GenPart 28 Jan 2009 • 5 min read

SPB 16.2 , TOC , table of contents , PCB design

Tech Tip: Avoiding "Error! Integer Overflow" With Incisive Simulator

While simulating a VHDL design with Incisive Simulator, if an integer overflow is…

adua 28 Jan 2009 • 1 min read

NCVHDL , Functional Verification , Incisive Enterprise Simulator (IES) , IES

"ClubT" Newsletter Issue #3 Just Posted

Specmaniacs and Other Trailblazers, The latest edition of the 'ClubT ' newsletter…

teamspecman 27 Jan 2009 • less than a min read

IEEE 1647 , SystemVerilog , IntelliGen , Low Power , Specman , HW/SW , verification strategy , Verification methodology , metric driven verification (MDV) , Functional Verification , Cadence VIP portfolio , Testbench simulation , OVM , VIP , OVM e , Coverage-Driven Verification , CDV , Multi-domain verification: HW/SW co-verification , e , Enterprise Manager , Enterprise Planner , ISX (Incisive Software Extensions) , Plan and metrics management , coverage driven verification (CDV) , Aspect Oriented Programming , ISX , System Verification , Incisive Enterprise Simulator (IES) , IES , AOP

SoC and IP

Low Latency DRAMs Continue to Serve Networking Niches

Low Latency DRAMs (LL DRAMs), Survive to Serve an Important Market Niche: Last…

Denali Blog 23 Jan 2009 • 4 min read

Allegro PCB SI at DesignCon

Drop by the Cadence booth at DesignCon to see the latest demonstrations of Allegro…

Maxwell86 23 Jan 2009 • less than a min read

PCB Signal and power integrity , IBIS-AMI , SerDes , PCB design , DDR3

Cadence SiP and IC Packaging at DesignCon

Those of you attending DesignCon in February should stop by the Cadence booth to…

Maxwell86 23 Jan 2009 • less than a min read

Digital SiP design , 3D-IC , TSV , IC Packaging & SiP design , IC Package Physical layout and co-design

RF Engineering

SpectreRF GUI Support for MMSIM 7.1

MMSIM 7.1 has just been released! The following IC release GUIs support the new MMSIM7…

Tawna 23 Jan 2009 • less than a min read

Virtuoso Spectre , Spectre RF , Virtuoso Spectre Simulator GXL , Virtuoso Spectre Simulator XL , Spectre , RF design

Digital Design

ST Microelectronics – A Fountain-head of Design Innovations

In my last blog, I asked all of you to send me your design innovations. Thanks for…

RahulD 22 Jan 2009 • 1 min read

SoC-Encounter , SoC-Encounter 8.1 , Digital Implementation , Encounter Digital Implementation , "SoC-Encounter"

Functional Verification More Important than Ever in 2009?

Here in Cadence Product Marketing, we're still recovering from our very busy annual…

tomacadence 22 Jan 2009 • 1 min read

metric driven verification (MDV) , Functional Verification , Formal Analysis , Coverage-Driven Verification , coverage driven verification (CDV) , OVM 2.0

3D IC or TSV: The Next Phase in Functional Density and Miniaturization

It seems that almost every semiconductor company is thinking or talking about 3D…

SiPper 22 Jan 2009 • less than a min read

Analog and RF SiP design , Digital SiP design , TSVi , IC Packaging & SiP design , IC Package Physical layout and co-design