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Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
• 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
cdns - all_blogs_categories

Blog - Post List
Latest blogs

Verification

DVCon 2013 for the Specmaniac

At the upcoming DVCon (in San Jose, CA February 25-28) , Cadence will cover all aspects…

• 3 min read
Specman , Specman/e , methodology , verification strategy , metric driven verification (MDV) , debug , Functional Verification , Formal Analysis , formal , Incisive Debug Analyzer , e , e language , Mike Stellfox , DVcon , Aspect Oriented Programming , simulation , AOP , verification

System, PCB, & Package Design 

Ease Your IC Packaging Documentation and Manufacturing Exports for Stacked Dies in…

Following our last posting concerning intelligent documentation text, this week we…

• 2 min read
documentation , stacked dies , package , SiP , IC Package , IC Packaging , packaging , cadence , manufacturing exports , Digital SiP design , 16.6 , IC Packaging and SiP , APD , wirebonds , IC Packaging & SiP design , SPB , Allegro Package Designer , IC packaging documentation , SiP Layout , wirebonding , Physical layout and co-design , wirebond profile library , cavity

Verification

Improve Debug Productivity - SimVision Video Series on YouTube

Most verification customers claim that they are spending over 50% of their verification…

• less than a min read
SystemVerilog , Low Power , : Functional Verification , transaction , watch window , metric driven verification (MDV) , cadence , debug , Functional Verification , Debug Performance , UVM-MS , RTL , simvision , Incisive Enterprise Simulator , SimVision watch window , EDA360 , Coverage-Driven Verification , Mixed Signal Verification , Incisive , Verilog , bug , sequences , RTL design , video tutorial , IEV , Incisive Enterprise Simulator (IES) , VHDL , debugging , IES , IFV , IES-XL

System, PCB, & Package Design 

What's Good About FSP Planning Mode? Check Out 16.6!

The Allegro FPGA System Planner (FSP) 16.6 release offers major improvements in Auto…

• 1 min read
PCB , PCB Layout and routing , Allegro 16.6 , net swap , Routing , FPGA-PCB Co-Design , FPGA System Planner , Placement Edit , FPGAs , PCB Editor , Front-end PCB design , design , FSP , pinswap , swap , PCB design , Design Entry , Grzenia , pin swap , FPGA , FPGA: PCB

Analog/Custom Design

Introduction to Cadence Virtuoso Advanced Node Design Environment

What can designers do about advanced node technology? This is an introduction to…

• 6 min read
STI , Virtuoso Advanced Node , length of diffusion , custom/analog , Routing , analog prototyping , Double Patterning , layout-dependent effects , Ishikawa , custom , odd-loop marker , 20nm , Advanced Node , module generation , analog , WPE , design flow , LDE , dynamic coloring , LOD , well proximity , Placement , stress , interconnect layers , Custom IC Design , local interconnect

Verification

A Concrete Linux Virtual Platform Example

Virtual platforms are used to find many different types of system and software issues…

• 3 min read
Device Drivers , zynq , virtual platforms , virtual prototypes , UART , embedded software , Ubuntu , softtware bugs , SystemC , xilinx , Zynq virtual platform , debugging software , linux , Jason Andrews , Zynq-7000 , System Design and Verification

Verification

A 10-year Look-Back from 2013 – Some Technology Predictions that are Coming True…

It is January 2013, the year has begun and it is time for my annual 10 year look…

• 4 min read
SystemVerilog , Apple , Low Power , integration , Google Glass , virtual platforms , tungsten , GPS , Cell Phone , base stations , MP3 , virtual prototypes , IBM , Harry Goldstein , PDA , abstraction , google , Linda Geppert , 10 year , Palm , hardware/software CoDesign , 10 year look-back , software , IEEE Spectrum , Mark. E. Dean , Schirrmeister , ESL , iPhone , ESL system-level design

System, PCB, & Package Design 

What's Good About DEHDL’s Interface Aware Design? The Secret's in the 16.6 Release

Components in a design communicate with each other based on some rules or protocols…

• 3 min read
interface aware design , PCB , PCB Layout and routing , constraints manager , Allegro 16.6 , DEHDL , signal grouping , hierarchical net groups , 16.6 , interface definitions , interfaces , PCB Editor , Design Entry HDL , PCB design , Grzenia , net groups , Allegro

Verification

Specman: An Assumed Generation Issue and its Real Root Cause

Random generation is always a complex task, and differences in results are usually…

• 2 min read
AF , IntelliGen , Specman , debug , Functional Verification , garbage collection , lists , Incisive , e code , Generation , e language , assumed generation , Funcional Verification , Zander , vManager , random generation

System, PCB, & Package Design 

Make Your IC Packaging Documentation Labels Smarter with 16.6 SiP and APD

Documentation is key when completing any IC package substrate design. Without it…

• 3 min read
package , IC Package , IC Packaging , packaging , Digital SiP design , 16.6 , IC Packaging and SiP , APD , IC Packaging & SiP design , Allegro Package Designer , APD 16.6 , Physical layout and co-design

Verification

2013 CES: Top 4 Trends Benefiting EDA

While a variety of EDA customer segments are growing, consumer electronics continues…

• 5 min read
Automotive , mobile devices , Verification IP , Design IP , Joe Hupcey III , IP , Consumer Electronics Show , CES , 14nm , SoC , apps , UltraHD TVs , verification

System, PCB, & Package Design 

What's Good About Viewing Constraint Differences? See for Yourself in Allegro 16

Starting with the Allegro PCB Editor 16.6 release, we can compare two constraint…

• 2 min read
PCB , PCB Layout and routing , constraint databases , Allegro 16.6 , 16.6 , PCB Editor , viewing constraint differences , constraint difference , PCB design , Constraints , Grzenia , comparing constraints , Allegro PCB Editor , Allegro

Digital Design

Five-Minute Tutorial: Creating An EM Model File

One of the least-fun parts of running power and rail analysis has always been coming…

• 2 min read
EDI , electromigration , rail analysis , EM Model , ICT , iRCX , EPS , Power Analysis , five minute tutorial

Analog/Custom Design

Virtuosity: 10 Things I Learned in December By Browsing Cadence Online Support

In addition to the R&D engineers who actually develop our software, the folks in…

• 4 min read
Variability Aware Design , AMS , Analog Design Environment , Virtuoso IC6.1.5 , Virtuoso Space-based Router , VSR , Analog Simulation , Cadence Space-based Router , workshop , IC615 , IC 6.1.5 , ADE , Mixed-Signal , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , Analog Design Environment , Schematic Editor , ViVA , ADE-XL , mixed signal , Custom IC Design , Virtuoso Layout Suite

Analog/Custom Design

Library "Safe Margins" -- Are They Really Saving Your Design?

Designers need to radically re-think their strategies for timing closure to get the…

• 4 min read
Standard Cell , memory characterization , Process Variation , Elzeftaki , library characterization , Timing Closure , Complex IO , PVT corners , safe margins , Complex Cell

Analog/Custom Design

SKILL for the Skilled: Part 6, Many Ways to Sum a List

In a previous post I presented sumlist_2b as a function that would sum lists of length…

• 5 min read
Team SKILL , programming , Jim Newton , sum a list , IC615 , SKILL for the Skilled , summing , Lisp , SKILL++ , SKILL

System, PCB, & Package Design 

Customer Support Recommended – Pin Swapping in Allegro Design Entry CIS and PCB …

Placement and routing have always been an integral part of printed circuit board…

• 4 min read
capture , "capture CIS" , SPB16.3 , Allegro Design Entry , Allegro 16.6 , customer support , PCB design" , net swap , Design Entry CIS , OrCAD Capture Marketplace , Routing , OrCAD Capture , 16.6 , Allegro 16.3 , SPB 16.3 , Capture CIS , Capture-CIS , Allegro 16.5 , Allegro 16.2 , SPB16.2 , Appnote , pinswap , "PCB design" , OrCAD , swap , 16.5 , Design Entry , SPB16.5 , Allegro PCB Editor , pin swap , application note , OrCAD PCB Editor , library , PCB Capture , Schematic

Analog/Custom Design

Revamped Mixed-Signal Solutions Portal Reflects Cadence Leadership and Commitmen…

Cadence holds a leading position in the EDA industry due to its broad product portfolio…

• 1 min read
CDNLive , cadence , AMS Designer , custom , Design Challenges , analog , web page , Mixed-Signal Methodology Guide , Mixed-Signal , Mixed-signal solutions web page , Virtuoso , mixed-signal book , digital , implementation , mixed signal , Encounter Digital Platform , web site , verification

Verification

Specman: Determining a Good Value for optimal_process_size

Specman's Automatic GC Settings mechanism is aimed at eliminating the need for users…

• 7 min read
AF , memory usage , optimal_process_size , Specman , garbage collection , Functional Verification' signal integrity , e language , optimal process size , memory consumption , OPS
CDNS - Fix Layout Hompage