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Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
• 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
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Blog - Post List
Latest blogs

Verification

iPhone5 Differentiation is Chip Design

In case you may have missed it, Apple recently launched a new iPhone. As per the…

• 5 min read
High-Level Synthesis , Apple , TLM , RTL , android , iPhone5 , Samsung , SoC , C-to-Silicon , software , smartphones , ARM , ESL , iPhone , Audience

Verification

Using a Network File System with the Xilinx Zynq-7000 Virtual Platform

There are a number of ways to do embedded software development for Xilinx Zynq-7000…

• 5 min read
Ubuntu 12.04 , Zynq virtual platform , Network File System , Embedded Linux

Analog/Custom Design

SKILL for the Skilled: Part 3, Many Ways to Sum a List

In Part 1 and Part 2 of this series of posts, I showed a couple of ways to sum up…

• 4 min read
recursive functions , Team SKILL , Jim Newton , sum a list , SKILL for the Skilled , recursion , Virtuoso , Lisp , Custom IC Design , SKILL++

Verification

Accelerated VIP Delivers Value for Firmware/Driver Validation and Integration

Earlier this year, Cadence announced the expansion of its VIP Catalog to include…

• 2 min read
validation. , Driver , firmware , System Design & Verification

Verification

Lessons for EDA When Low Power vs. Heat Dissipation Isn’t a Fair Fight: A Case Study…

Right up there with functional verification, the challenges of low power design and…

• 3 min read
uvm , Low Power , GoPro Hero2 , thermal verification , Functional Verification , MCAD , video , mechanical design automation , EDA , low-power design , thermal behavior , heat dissipation

System, PCB, & Package Design 

What's Good About ADW’s Flow Manager? Check out the 16.5 Release and See!

The 16.5 Allegro Design Workbench (ADW) Flow Manager has been enhanced to provide…

• 1 min read
PCB , data management , symbol editor , flow manager , Allegro Design Workbench , Library flow , Team design , Allegro 16.5 , Library and design data management , SPB , Design Entry HDL , design data management , symbol , design , PCB design , Design Entry , Grzenia , SPB16.5 , Librarians , library , ADW , Schematic , Allegro

Analog/Custom Design

SKILL for the Skilled: Part 2, Many Ways to Sum a List

In the previous posting, SKILL for the Skilled: Many Ways to Sum a List (Part 1 …

• 4 min read
Team SKILL , Jim Newton , sum a list , summing , Virtuoso , software development , SKILL++ , SKILL

Digital Design

Simple Steps to Debug DRC Violations Undetected in EDI System

You've placed and routed your design in the Encounter Digital Implementation (EDI…

• 4 min read
EDI , DRC , design rules , DRC signoff , LEF , Cadence Online Support , NanoRoute , encounter , Digital Implementation , Encounter Digital Implementation , Verify Geometry , PVS , DRC violations , debug DRC violations

Analog/Custom Design

Things You Didn't Know About Virtuoso: The (Setup) State of Things

Apologies for the long delay between articles (best intentions and all that). I last…

• 3 min read
Variability Aware Design , Analog Design Environment , Virtuoso IC6.1.5 , setup states , IC615 , analog , IC 6.1.5 , ADE , Virtuoso Analog Design Environment , Virtuoso , ADE-GXL , Analog Design Environment , ADE-XL , Custom IC Design

Analog/Custom Design

SKILL for the Skilled: Part 1, Many Ways to Sum a List

A while back I presented a one day SKILL++ seminar to a group of beginner and advanced…

• 3 min read
Jim Newton , sum a list , summing , Virtuoso , apply , software development , SKILL++ , sumlist , SKILL

Verification

UVM Testflow Phases, Reset and Sequences

In this post, we will discuss the interesting challenge of reset during simulation…

• 2 min read
AF , uvm , Specman , BFM , Testflow , Functional Verification , testflow phases , e language , team specman , sequences , Reset mechanism , Shneydor , verification , sequence driver

Verification

What Does it Take to Migrate from e to UVMe?

So you are developing your verification environment in e , and like everyone else…

• 3 min read
IEEE 1647 , SystemVerilog , scoreboard , uvm , Specman , Specman/e , UVM e , vr_ad , UVM-e , advanced verification , e language , UVC , SCE-MI , team specman , Constraints , Aspect Oriented Programming , sequences , Incisive Enterprise Simulator (IES) , Shneydor , AOP

System, PCB, & Package Design 

What's Good About DEHDL’s Find Functionality? The Secret's in the 16.5 Release!

The current Allegro Design Entry HDL (DEHDL) Page Search toolbar works only on the…

• 3 min read
DEHDL find , page search , hierarchy , flat schematics , super filter , selection filters , property changes , Allegro 16.5 , Design Entry HDL , Find result , design , Design Entry , Grzenia , highlighting , SPB16.5 , ConceptHDL , PCB Capture , Schematic , Allegro

Verification

Introduction to the Linux Kernel Message System

One of the most common problem reports related to Virtual Platforms running Linux…

• 6 min read
Virtual System Platform , virtual platforms , GDB , VAP , cadence , ring buffer , uncompressing Linux , virtual prototypes , booting Linux , embedded software , VSP , Imperas , software development , Zynq virtual platform , linux , Zynq-7000 , Embedded Linux , ESL , System Design and Verification , kernel messaging system , Andrews

System, PCB, & Package Design 

What's Good About PCB SI Adaptive Mesh Generation? 16.5 Has Many New Enhancements

The 16.5 PCB SI product’s rectangular mesh scheme is used for shapes, cutouts, slots…

• 2 min read
PCB SI , PCB , SI , PI , PCB PI , PDN , Signal Intregrity , SI bus analysis , SigXP UI , PCB Signal and power integrity , "PCB SI" , High Speed , Allegro 16.5 , SPB , High-Density Interconnect , full wave , Signal Integrity , full-wave , PDN Analysis , OrCAD PCB SI , field solver , Allegro PCB SI , PCB design , "PCB PI" , adaptive mesh generation , Grzenia , SPB16.5 , SI analysis and modeling , Meshing , HDI , Allegro

Analog/Custom Design

Mixed Signal Design IP Embraces Metric-Driven Verification Using RNM

Even though it's been over 2 months since this year's Design Automation Conference…

• 3 min read
real number modeling , DAC , uvm , IP , A/MS , Verilog-AMS , analog , co-simulation , Mixed-Signal , analog behavioral models , analog/mixed-signal , model validation , RNM , metric-driven verification , VHDL-AMS , assertions , mixed signal , mixed-signal design , wreal , real number models , Design Automation Conference , SPICE , mixed-signal verification , verification , stmicroelectronics , real number

System, PCB, & Package Design 

Customer Support Recommended – Appnote on Implementing the Force-Sense Kelvin Co…

The use of separate force (F) and sense (S) connections (often referred to as a Kelvin…

• 2 min read
PCB , Kelvin connection , Allegro Design Entry , customer support , part developer , DEHDL , PDV Symbol , Allegro 16.5 , Appnotes , PCB Editor , Design Entry HDL , Appnote , symbol , Force-Sense , PCB design , 16.5 , force sense , SPB16.5 , ConceptHDL , application note , Schematic , Allegro , Kelvin

System, PCB, & Package Design 

What's Good About APD’s Wire Bond Settings Groups? You’ll Need the 16.5 Release to…

The 16.5 Allegro Package Design (APD) product has been modified to provide a different…

• 4 min read
PCB , PCB Layout and routing , packaging , APD , Allegro 16.5 , Wirebond , Allegro Package Designer , wire bond settings groups , PCB design , Grzenia , wire bond , Allegro

Verification

Report From Silicon Valley With Application Engineer Bin Ju

Luckily I was able to track down my very busy colleague Bin Ju between assignments…

• less than a min read
Joe Hupcey III , ABV , Formal Analysis , Bin Ju , formal , video , formal apps
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