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Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
• 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
• 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
• 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
• 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's Good About Relational Table Support in Capture-CIS? You'll Need SPB16.2 to

With SPB16.2 release, Capture-CIS allows you to create and use relational tables…

• 2 min read
SPB 16.2 , Functional Verification , Capture-CIS , RDBMS , Allegro

Analog/Custom Design

Getting a Feel for RF

It was a delight when I read the blog by Bill Schweber of TechOnline's RF DesignLine…

• 2 min read
MMSIM , Virtuoso Analog Design Environment , Virtuoso , RF design , Circuit Design , Simulators , Custom IC Design

SoC and IP

Industry Downturn Perspectives..Forward and Backward

Recent Results Signal Better Times Ahead; How Much Better?...Little Consensus,…

• 9 min read

Verification

Performance-Aware e Coding Guidelines – Part 5

In this last segment of the series on performance-aware coding, allow me to share…

• 2 min read
IEEE 1647 , performance , events , Specman , Functional Verification , API , tech tips , OVM , OVM e , e , temporal expressions , OVM-e , specman elite , IES , IES-XL

RF Engineering

2009 RFIC Symposium in Boston - Are You Going?

If you are an RFIC designer then I hope you are planning on attending the 2009 RFIC…

• 2 min read
RFIC , Virtuoso Spectre Simulator XL , spectreRF , Spectre , RF design , Circuit Design , harmonic balance , wireless integrated circuit verification

Digital Design

VoltageStorm Is Alive and Kicking!

If your only news source were some of the common EDA pundits, you would likely believe…

• 2 min read
timing system , ets , voltagestorm , EPS , Digital Implementation , encounter power system

Digital Design

WiMAX and the Road to Complete Independence From Network Cables: Sequans Communication…

Step into any Starbucks hotspot or Wi-Fi cafe, and you'll see something that was…

• 3 min read
Low Power , encounter 8.1 , Power-Efficient Design , SoC-Encounter" , Cadence Encounter Power System , Digital Implementation , The Power Forward Initiative , Encounter Digital Implementation , Encounter Digital Implementation System 8.1

Verification

Quick Tip - New Home For the "SVM" Docs

FAQs: What happened to the "SVM" documentation, and to SVM in general? Has SVM been…

• 1 min read
IPCM , Functional Verification , OVM , SVM , Incisive , eRM

System, PCB, & Package Design 

What's Good About Social Networking? Boomer Adoption up, Gen Y Flat

I decided to switch gears a bit and write about an interesting article I read in…

• 1 min read
social networking , Baby Boomers , PCB design , Generation Y , EE Times

RF Engineering

Spectre RF By Any Other Name ...

It has been a while since I last appende d , hope you are well! It was a little…

• 1 min read
DAC , ADC , Spectre RF , RF design

RF Engineering

Setting VIVA Waveform Color Defaults When Using ADE

I found myself getting a little bit frustrated with some of the default colors that…

• less than a min read
MMSIM71 , Virtuoso Spectre , spectreRF , Spectre , RF design

Analog/Custom Design

OpenAccess, Its Just a Database…

I suspect that in another year we’ll all stop talking about OpenAccess (OA) like…

• 3 min read
ecosystem , Virtuoso Analog Design Environment , Virtuoso , PDK , Custom IC Design , Process Design Kit , custom design technology

Verification

CtoS support of Multiple Clocks

In a previous blog entry we discussed C-to-Silicon’s (CtoS’s) ability to support…

• less than a min read
High-Level Synthesis , CTOS , clock , System Design & Verification , SystemC , C-to-Silicon Compiler , clocking

Verification

Totally Off Topic: It's A Girl!

Allow me to digress from EDA subjects to herald the birth of my first child! …

• less than a min read
baby , Functional Verification , team specman , girl

Verification

Embedded Software on the Virtual Platform: Analog or Digital?

One of the things I learned when Verisity purchased Axis was the difference in mindset…

• 4 min read
Specman , virtual platform , System Design and Verification , analog , Enterprise Manager , waveform , functional coverage , ISX , check pointing , Jason Andrews

Verification

The Cadence ESL Machine Keeps Building Momentum!

Last week EDN named Palladium DPA a 2009 EDN Innovation Award Winner , and C-to-Silicon…

• 3 min read
System Design and Verification , Palladium , EDN , C-to-Silicon , EDN Innovation award

Verification

Performance-Aware e Coding Guidelines – Part 4

Specman 8.2s3 contains a new API to the sequence driver that enables users to improve…

• less than a min read
IEEE 1647 , performance , Specman , Functional Verification , API , tech tips , OVM , OVM e , e , OVM-e , specman elite , sequences , IES , IES-XL

System, PCB, & Package Design 

What's Good About TCL, P&S, STUFF in ASA? The Secret's in the SPB16.2 Release!

OK - so maybe I got a little bit too happy with acronyms (STUFF doesn't represent…

• 3 min read
ActiveTcl , SCM , SPB 16.2 , ASA , PCB design , Allegro , tcl

Verification

C-to-Silicon Support of Concurrent Processes

Another key differentiator of C-to-Silicon Compiler (CtoS) when compared to C …

• less than a min read
High-Level Synthesis , CTOS , TLM , System Design and Verification , SystemC , ESL
CDNS - Fix Layout Hompage