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Corporate News

Cadence Celebrates 20 Years in Pune, Reinforces Long-Term R&D Commitment

Cadence, a global leader in electronic system design, is celebrating 20 years in…

Corporate
• 1 min read
news story , featured , Cadence Culture

Cadence Japan

ケイデンス、TSMC N3Pテクノロジーで64Gbps対応UCIe IPソリューションをテープアウト

ケイデンス、第3世代UCIe IPをTSMC N3Pでテープアウト。64Gbps対応でAI/HPC向けマルチダイ設計を加速、業界最高水準の帯域密度を実現。

Cadence Japan
• less than a min read
news story , ucie , featured , chiplets , TSMC N3P

Analog/Custom Design

Virtuoso Studio IC25.1 ISR3 Now Available

Virtuoso Studio IC25.1 ISR3 production release is now available for download.

KomalJohar
• 4 min read
IC25.1 , featured , Cadence blogs , Virtuoso Studio , IC Release Announcement blog

Corporate News

Cadence Tapes Out UCIe IP Solution at 64G Speeds on TSMC N3P Technology

Delivering the next wave of chiplet innovation, Cadence has successfully taped out…

Corporate
• 2 min read
news story , ucie , featured , chiplets , TSMC N3P
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Blog - Post List
Latest blogs

Verification

Dealing with the "Throw it Over the Wall" Methodology in Power Supply Network De…

"Throw it over the wall" is business slang for completing your part of a project…

• 2 min read
PSN , Power Supply Network , debug , Functional Verification , power-aware , UPF

Verification

Searching Through a Complex Design? DFS to the Rescue!

Recently, while at a customer site, I was faced with the huge task of looking for…

• 4 min read
Functional Verification , simvision , design file search , Incisive Enterprise Simulator (IES)

Whiteboard Wednesdays

Whiteboard Wednesdays—Lower BOM Cost, Use 32-bit Wide LPDDR4 in Consumer Applica…

In this week's Whiteboard Wednesdays video, the second of a two-part series, Jeffrey…

• less than a min read
Whiteboard Wednesdays , IP , LPDDR4 , 32-bit

SoC and IP

Cadence at CES 2015: Power-Sensitive Always-On Systems

LAS VEGAS—As the mobile world matures, opportunities abound for optimizing the user…

• less than a min read
audio , power management , HiFi Mini , Tensilica , Realtek Semiconductor , HiFi DSP , CES 2015

Verification

Lazy Test Cases for Tool Failures Using the Testcase Optimizer (TCO)

The Current State It seems to be a fact of life that software has bugs and, unfortunately…

• 7 min read
performance , methodology , verification strategy , debug , tech tips , Incisive , universal verification methodology , verification

SoC and IP

Cadence at CES 2015: A Look at Face-Detection Technology

LAS VEGAS—A key function of automotive, IoT, security, and similar applications is…

• less than a min read
IP , cadence , IVP , Xtensa , CES 2015 , image processing , video processing

Whiteboard Wednesdays

Whiteboard Wednesdays—New LPDDR4 Standard Features

In this week's Whiteboard Wednesdays video, the first of a two-part series, Jeffrey…

• less than a min read
Whiteboard Wednesdays , LPDDR4 , DBI , LVSTL

SoC and IP

Cadence at CES 2015: The IP Story

LAS VEGAS—The annual International Consumer Electronics Show (CES) here is not just…

• less than a min read
ip cores semiconductor IP , EDA companies , Martin Lund , IP design , CES 2015

SoC and IP

My Top 10 List from CES

After nearly a week at CES, almost everyone is asking me – what was the big thing…

• 4 min read
DSP , Design IP , IP , CES , audio , video , IoT , HiFi , ip cores , Tensilica , semiconductor IP , Internet of Things , imaging

System, PCB, & Package Design 

Customer Support Recommended—Modeling Voltage-Controlled Oscillators (VCO) Using…

A voltage-controlled oscillator (VCO) is an electronic oscillator whose oscillation…

• 2 min read
AMS , Allegro 16.6 , Allegro 16.5 , PSPICE , PCB design , SPB16.5

Whiteboard Wednesdays

Whiteboard Wednesdays—Soundwire Audio Interface

In this week's Whiteboard Wednesdays video, the first of a two-part series, Charles…

• less than a min read
Whiteboard Wednesdays , IP , audio , MIPI , Soundwire

System, PCB, & Package Design 

What's Good About OrCAD Capture’s Customization Capabilities? 16.6 has Several New…

The 16.6 release of OrCAD Capture/Capture-CIS provides several areas for you to customize…

• 2 min read
OrCAD Capture , 16.6 , Capture CIS , Grzenia , Schematic

Verification

Using Generative List Pseudo Methods in Constraints – A Case Study

This article highlights the use of list pseudo-methods constraining the content of…

• 2 min read
Specman , list pseudo-methods , Ethernet , constraint coding , debugging

SoC and IP

Cadence at CES 2015: Experience Integrated Solutions for Mobile

Given that CES is a novelty-focused event, it is crucial that innovative companies…

• 2 min read
Design IP , cadence , Consumer Electronics Show , CES , DIP , DSI , Tensilica , CES 2015 , MIPI D-PHY

Verification

Connected Field Sets – What Are Those and Why Should I Care?

Right form the start Specman has been very good at generating constrained random…

• 4 min read
connected field sets , Specman , modeling constraints , IntelliGen constraint solver , Constraints , debugging

SoC and IP

Driven by Mobile, LPDDR4 Poised to Step Up

SANTA CLARA, Calif.—In the long and storied history of semiconductor memories, the…

• 2 min read
IP , DDR4 , MemCon 2014 , IoT , IP integration , memory IP , ip cores , future of IP

Whiteboard Wednesdays

Whiteboard Wednesdays—SoC Interconnect Verification

In this week's Whiteboard Wednesdays video, Tom Hackett discusses the VIP Catalog…

• less than a min read
Verification IP , Interconnect Workbench , Whiteboard Wednesdays , Interconnect Validator , VIP , verification

Verification

Updates from the UVM Multi-Language (ML) Front

An updated version of the UMV-ML Open Architecture library is now available on the…

• 1 min read
funtional verification , SystemVerilog , UVM-ML , UVMWorld , UVM multi-language , e , SystemC

Analog/Custom Design

Top 5 Issues that Make Things Go Wrong in Mixed-Signal Verification

Key Findings : There are a host of issues that arise in mixed-signal verification…

• 5 min read
MS , uvm , Metric-Driven-Verification , Palladium , Mixed Signal Verification , Incisive , MDV-UVM-MS , Virtuoso , mixed signal , MDV
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