• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Cadence Blogs

Stay up to date with our latest corporate and technology blog posts

Explore the Cadence Forums to find and exchange in-depth technical information.

  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

    Popular Search: Corporate NewsArtificial IntelligencePCB DesignCFD
Featured

Life at Cadence

Cadence Giving Foundation Leads a Day of Collective Community Impact

On June 25, the Cadence Giving Foundation brought together an extraordinary coalition…

Corporate
Corporate 30 Jun 2026 • 2 min read
Cadence Giving Foundation , featured , san jose , Collective Impact Day , City Year Bay Area

Corporate News

The Three Phases of AI Adoption

Artificial intelligence is often discussed as if the industry is moving through a…

Corporate
Corporate 25 Jun 2026 • 6 min read
featured , infrastructure ai , agentic ai , physical ai , sciences ai

Corporate News

Finding What Truly Moves You: Honoring Alberto Sangiovanni-Vincentelli

"Finding what truly moves you is happiness. Success is measured in the lasting impact…

Corporate
Corporate 24 Jun 2026 • 2 min read
featured , EDA , Alberto Sangiovanni-Vincentelli , UC Berkeley

Corporate News

Accelerating Drug Discovery with Agentic AI and Computational Science

By Louis Culot, corporate vice president and general manager, Cadence Molecular Sciences…

Corporate
Corporate 23 Jun 2026 • 3 min read
drug discovery , Cadence Molecular Sciences , featured , agentic ai , NVIDIA
cdns - all_blogs_categories

  • All 6438
  • Corporate News 266
  • Life at Cadence 206
  • Academic Network 169
  • Analog/Custom Design 804
  • Artificial Intelligence 28
  • Cloud 24
  • Computational Fluid Dynamics 375
  • Data Center 60
  • Digital Design 465
  • Learning and Support 63
  • RF Engineering 116
  • SoC and IP 435
  • System, PCB, & Package Design  1017
  • Verification 1332
  • Cadence Japan 18
  • Physical Systems Simulation 25

  • CFD(数値流体力学) 45
  • 中文技术专区 9
  • カスタムIC/ミックスシグナル 199
  • PCB、IC封装:设计与仿真分析 136
  • PCB解析/ICパッケージ解析 44
  • PCB設計/ICパッケージ設計 61
  • RF /マイクロ波設計 45
  • Spotlight Taiwan 64
  • The India Circuit 93
  • 定制IC芯片设计 79
  • データセンター 7

  • Whiteboard Wednesdays 253
Blog - Post List
Latest blogs

Breakfast Bytes

What Is Automotive Tool Confidence Level 1?

ISO 26262 is the functional safety standard for automotive, as you probably already…

Paul McLellan 10 Nov 2016 • 4 min read
tcl1 , tool confidence level , ISO 26262 , Breakfast Bytes , tcl

Breakfast Bytes

What's For Breakfast? Video Preview November 14th to 18th

https://youtu.be/OQ1c30nbD0s Monday: Red Hat's Jon Masters talks about ARM…

Paul McLellan 9 Nov 2016 • less than a min read
Automotive , ARM Techcon , Jasper User Group , risc-v , NXP , jasper gold , JUG , formal , risc-v foundation , google , red hat , Jasper , open source , mobile , ISO 26262 , ARM , linux , Formal verification , verification

Breakfast Bytes

Moore and Medical at ARM TechCon

The second keynote on the first day of ARM TechCon was a double act with Greg Yeric…

Paul McLellan 9 Nov 2016 • 7 min read
security , greg yeric , ARM Techcon , IoT , 28nm , 3nm , 5nm7nm , Mike Muller , medical , moore's law , privacy , ARM , Breakfast Bytes , 2nm

Whiteboard Wednesdays

Whiteboard Wednesdays - Industry Trends and Requirements for Autonomous Driving

In this week's Whiteboard Wednesdays video, the first in a three part series focusing…

References4U 8 Nov 2016 • less than a min read
Automotive , Whiteboard Wednesdays , functional safety , automotive electronics

Breakfast Bytes

Who Wrote the Book on Formal Verification?

Who wrote the book on formal verification? Depending on whether you want to take…

Paul McLellan 8 Nov 2016 • 5 min read
Intel , Jasper User Group , JUG , formal , CDC , Jasper , property checking , Equivalence Checking , jug 2016 , clock domain crossing , ARM , Breakfast Bytes , Formal verification , verification

Analog/Custom Design

Virtuoso Video Diary: I Am Not Promoting Layout Hierarchy Manipulation!

Are you contemplating manipulating your layout hierarchy by adding or removing a…

Rishu Misri Jaggi 7 Nov 2016 • 5 min read
Flatten , Transparent instances , Virtuoso Video Diary , Connectivity-driven , Make Cell , XL-compliance , Layout hierarchy manipulation , Custom IC Design , Virtuoso Layout Suite XL

Breakfast Bytes

The Amazing Raspberry Pi Story

Eben Upton gave a spellbinding keynote at ARM TechCon on the history of Raspberry…

Paul McLellan 7 Nov 2016 • 9 min read
BBC , Raspberry Pi , Cambridge , acorn , british broadcasting corporation , ARM , Breakfast Bytes

Breakfast Bytes

Automotive Security: A Hacker's Eye View

Charlie Miller gave a keynote at ARM TechCon on automotive security. He is regarded…

Paul McLellan 4 Nov 2016 • 8 min read
security , Automotive , onstar , uber , jeep , chris valasek , charlie miller , tesla , wired magazine , Breakfast Bytes

Verification

Analog Devices Promotes Portable Stimulus at DVClub

If you’re not familiar with the series of DVClub events held in North American, Europe…

tomacadence 3 Nov 2016 • 3 min read
Analog Devices. ADI , pswg , cadence , debug , System Design and Verification , Dave Brownell , software , Accellera , System Design & Verification , portable stimulus , System Design and Verification , verification

Breakfast Bytes

What's For Breakfast? Video Preview November 7th to 11th

https://youtu.be/n4jz8shM1hM Monday: The amazing story of Raspberry Pi as…

Paul McLellan 3 Nov 2016 • less than a min read
security , Automotive , greg yeric , ARM Techcon , Jasper User Group , Low Power , trustzone , Raspberry Pi , jasper gold , palladium z1 , eben upton , JUG , IoT , tcl1 , Palladium , Jasper , Mike Muller , medical , Internet of Things , Power Analysis , ISO 26262 , ARM , Formal verification

System, PCB, & Package Design 

How to Address the Challenges of Serial Link Design and Analysis

What is a serial link? It's an interface where data is serialized for high-speed…

Sigrity 3 Nov 2016 • 3 min read
Serial link analysis , PCB , SI , IBIS-AMI , Signal Integrity , Sigrity , High Speed design , Allegro

Breakfast Bytes

Automotive Is a Pot of Gold Guarded by a Dragon

One of the big themes of pretty much any conference on semiconductors these days…

Paul McLellan 3 Nov 2016 • 6 min read
Automotive , functional safety , tool confidence level , DVcon , DVCon Europe , ISO 26262 , optima , Breakfast Bytes

Whiteboard Wednesdays

Whiteboard Wednesdays - Optimized FFTs on the Tensilica ConnX BBE32EP DSP

Fast Fourier transform (FFT) is a key kernel in almost all DSP applications, and…

References4U 2 Nov 2016 • less than a min read
DSP , Whiteboard Wednesdays , baseband , ConnX , radar , Tensilica , signal processing , FFT

Verification

Genie in a Mouse Click: Indago Protocol Debug App

Do you remember what life was like before the internet and smart phones? If you wanted…

Priyab 2 Nov 2016 • 4 min read
Productivity Tool , Verification IP , and Verification IP' , VIP , Indago Protocol Debug App , design , 'Tensilica

Breakfast Bytes

Wave Computing: a Dataflow Processor for Deep Learning

On the first day of the Linley Processor conference someone told me that he was really…

Paul McLellan 2 Nov 2016 • 4 min read
deep learning , tpu , wave computing , DPU , tensor flow , dataflow computing , Breakfast Bytes , dataflow processor

Breakfast Bytes

Segars and Son

When I was growing up, there was a TV show in the UK called Steptoe and Son, and…

Paul McLellan 1 Nov 2016 • 5 min read
ARM Techcon , Simon Segars , IoT , masayoshi son , Internet of Things , arm holdings , ARM , Breakfast Bytes

Academic Network

Students from Tsinghua University Visit Cadence Beijing

On October 20, 2016, 12 Masters and Ph.D. students mostly from Institute of Microelectronics…

Tracy Zhu 31 Oct 2016 • less than a min read
Cadence Academic Network

System, PCB, & Package Design 

Why Move Up to Allegro 17.2-2016? Arc-aware routing with enhanced contour hug saves…

Enhanced Contour Routing is a new prototype feature in the Cadence® Allegro® PCB…

edhickey 31 Oct 2016 • 1 min read
Allegro 17.2 , Routing , Rigid-Flex , PCB design , Allegro PCB Editor , Why Move Up to 17.2

Breakfast Bytes

Automotive at Linley: Intelligent Vehicles and Intelligent Intersections

The whole afternoon the second day of the Linley Processor Conference was dedicated…

Paul McLellan 31 Oct 2016 • 5 min read
Automotive , NXP , linley processor conference , tensilica vision , mike demler , Automotive Ethernet , Linley , autonomous vehicles , Breakfast Bytes
<>
CDNS - Fix Layout Hompage

© 2026 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information