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Digital Design

Cadence RTL Design Studio: Built for the Full PPAC Journey

If you've used Joules RTL Design Studio, you already know what it can do. Now it…

raquelp
• 2 min read
Digital Design and Signoff , featured , Joules , Digital Implementation , rtlstudio

Corporate News

How the New ASK AI Assistant Makes Support More Seamless

Finding the right answer often takes more than one question. Users may start with…

Corporate
• 2 min read
featured , customer support , Generative AI , ASK Portal , ASK AI Assitant

Artificial Intelligence (AI)

You'll Still Do the Work—You Just Won't Do the Boring Part

Agentic AI is about to change your flow. Here's what actually shifts—and why the…

Corporate
• 5 min read
artificial intelligence , featured , agentic ai , NVIDIA , AI for design

Artificial Intelligence (AI)

The Feedback Loop Is the Moat

Every verification and design team I talk to is building agents right now. The demos…

Hamid Shojaei
• 14 min read
featured , AI in chip design , GenAI , AI/ML
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Blog - Post List
Latest blogs

Verification

OSCI Launches Video Tutorials for TLM 2.0

Cadence is one of the sponsors of a series of Open SystemC Initiative (OSCI) TLM…

• less than a min read
Intel , System Design and Verification , OSCI , TLM 2.0 , SystemC , interoperability , Modeling

Analog/Custom Design

Jurassic Park IV: The Return of ANALOG

In the lab, no one can hear you scream! When I was getting my BSEE in the…

• 2 min read
analog , Incisive , encounter , Virtuoso , RF design , Custom IC Design

Digital Design

EDA Industry Stays Ahead of Technology Curve

The EDA Industry is the unsung hero behind for modern era electronic revolution since…

• 2 min read
DAC , EDI , Multi-Core , Virtuoso , Parallel rocessing , Digital Implementation , DFM

Digital Design

Interview with SiRF's Nigel Foley on Low-Power Design

Over the last three years, customers have been able to leverage the Cadence Low-Power…

• 4 min read
digital Implementationg , Low Power , encounter 8.1 , Low-Power , encounter , Logic Design , Digital Implementation , Encounter Digital Implementation , Encounter Digital Implementation System 8.1

Analog/Custom Design

An Efficient and Fast Verification Flow for Analog Designs Validation using Virtuoso…

The emergence of sub-micron technologies has enabled today’s designers to include…

• 1 min read
CDNLive , Virtuoso , Spectre , RF design , MDL

Verification

Using Macros for Repetitive Coding Tasks

For this post welcome guest blogger Hilmar van der Kooij. Hilmar is a Cadence Application…

• 5 min read
Specman , Functional Verification , tech tips , OVM , OVM e , Coverage-Driven Verification , team specman , Aspect Oriented Programming , macros , AOP

SoC and IP

Early Returns on 1Q09 Financials

Memory Companies Suffer More in 1Q09, but Future Looks Better...or so they say: …

• 4 min read

RF Engineering

Enhanced pnoise Algorithm to Compute Phase-Noise for VCOs with Bandgap Voltage R…

Accurate phase-noise characterization is critical in the design of RF and microwave…

• 1 min read
DC , MMSIM , IC Voltage , RF design , VCO

Verification

Some SystemC Perspectives - An Interview with Vincent Motel

I sat down with Vincent Motel recently, a long time Cadence employee, and one of…

• 7 min read
OVM , C-to-Silicon , System Design & Verification , SystemC: OCSI

System, PCB, & Package Design 

What's Good About Relational Table Support in Capture-CIS? You'll Need SPB16.2 to

With SPB16.2 release, Capture-CIS allows you to create and use relational tables…

• 2 min read
SPB 16.2 , Functional Verification , Capture-CIS , RDBMS , Allegro

Analog/Custom Design

Getting a Feel for RF

It was a delight when I read the blog by Bill Schweber of TechOnline's RF DesignLine…

• 2 min read
MMSIM , Virtuoso Analog Design Environment , Virtuoso , RF design , Circuit Design , Simulators , Custom IC Design

SoC and IP

Industry Downturn Perspectives..Forward and Backward

Recent Results Signal Better Times Ahead; How Much Better?...Little Consensus,…

• 9 min read

Verification

Performance-Aware e Coding Guidelines – Part 5

In this last segment of the series on performance-aware coding, allow me to share…

• 2 min read
IEEE 1647 , performance , events , Specman , Functional Verification , API , tech tips , OVM , OVM e , e , temporal expressions , OVM-e , specman elite , IES , IES-XL

RF Engineering

2009 RFIC Symposium in Boston - Are You Going?

If you are an RFIC designer then I hope you are planning on attending the 2009 RFIC…

• 2 min read
RFIC , Virtuoso Spectre Simulator XL , spectreRF , Spectre , RF design , Circuit Design , harmonic balance , wireless integrated circuit verification

Digital Design

VoltageStorm Is Alive and Kicking!

If your only news source were some of the common EDA pundits, you would likely believe…

• 2 min read
timing system , ets , voltagestorm , EPS , Digital Implementation , encounter power system

Digital Design

WiMAX and the Road to Complete Independence From Network Cables: Sequans Communication…

Step into any Starbucks hotspot or Wi-Fi cafe, and you'll see something that was…

• 3 min read
Low Power , encounter 8.1 , Power-Efficient Design , SoC-Encounter" , Cadence Encounter Power System , Digital Implementation , The Power Forward Initiative , Encounter Digital Implementation , Encounter Digital Implementation System 8.1

Verification

Quick Tip - New Home For the "SVM" Docs

FAQs: What happened to the "SVM" documentation, and to SVM in general? Has SVM been…

• 1 min read
IPCM , Functional Verification , OVM , SVM , Incisive , eRM

System, PCB, & Package Design 

What's Good About Social Networking? Boomer Adoption up, Gen Y Flat

I decided to switch gears a bit and write about an interesting article I read in…

• 1 min read
social networking , Baby Boomers , PCB design , Generation Y , EE Times

RF Engineering

Spectre RF By Any Other Name ...

It has been a while since I last appende d , hope you are well! It was a little…

• 1 min read
DAC , ADC , Spectre RF , RF design
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