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Verification

DAC 2015 – Join Us to Experience the Continuum of Verification and System Development…

The biggest yearly event in electronic design automation (EDA) is due to take over…

fschirrmeister 4 Jun 2015 • 8 min read

cadence , EDA , Moscone Center , DAC 2015 , verification , system development

Verification

It’s Time to Modernize Debug Data and It’s Happening at DAC

“The leading edge is 1 million gates.” That was the news when we approved IEEE Verilog…

Adam Sherer 4 Jun 2015 • 2 min read

Verdi , debug , simvision , VCs , Indago , Debussy , Questa , Incisive Enterprise Simulator (IES) , IES

Whiteboard Wednesdays

Whiteboard Wednesdays—What's a Configurable Processor?

In this week's Whiteboard Wednesdays video, Chris Rowen discusses the basics of Tensilica…

References4U 2 Jun 2015 • less than a min read

Whiteboard Wednesdays , IP , Chris Rowen , Tensilica , configurable processor

Digital Design

Five-Minute Tutorial: Innovus User Interface Tips

Hi Everyone, No doubt by now you have heard about the Innovus Implementation System…

Kari 2 Jun 2015 • less than a min read

UI , Digital Implementation , Innovus , five minute tutorial

Verification

How Ethernet Standards Are Born

I attend IEEE 802.3 Ethernet standards meetings and blog about them from time to…

ArthurM 1 Jun 2015 • 5 min read

Verification IP , 802.3bp , Ethernet standards , Automotive Ethernet , Ethernet , 802.3 , Marris

Verification

Multi-Language Verification Environment (#2) – Passing Items on TLM Ports, Using…

In the previous blog post , we created a simple multi-language verification environment…

teamspecman 1 Jun 2015 • 3 min read

IEEE 1647 , uvm , methodology , Functional Verification , e , universal verification methodology , e language , multi-language , verification

Verification

Multi-Language Verification Environment—Getting First Run in Few Minutes

Seems that by now, every one in the industry realizes that multi-language verification…

teamspecman 28 May 2015 • 2 min read

uvm , methodology , e , e language , UVC , multi-language

Verification

Specman deep_copy()—Creating Too Many Structs

This blog starts with a description of a debugging session of a mysterious behavior…

teamspecman 28 May 2015 • 3 min read

Specman , debug , e , Funcional Verification , ClubT

SoC and IP

Three Steps for USB Application Success – Design, Verify, Certify

With the USB protocol being so popular nowadays (and frankly speaking, was there…

Jacek Duda 27 May 2015 • 2 min read

Design IP , host , cadence , controller , PHY , OTG , USB , Dual Mode , ip cores , Dual Role , device

Whiteboard Wednesdays

Whiteboard Wednesdays - DDR4 Bank Grouping

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty continues his discussion…

References4U 26 May 2015 • less than a min read

Whiteboard Wednesdays , DDR4 , memory IP , DDR4 bank grouping

System, PCB, & Package Design

What's Good or Not So Good About Cadence Documentation? Here’s Your Chance to Let…

Most of our customers use the product documentation, Help, and Cadence Online Support…

Jerry GenPart 26 May 2015 • less than a min read

COS , Cadence Design Systems , Cadence Online Support , Cadence Help , Cadence documentation

SoC and IP

IP is BIG at the Design Automation Conference, June 7-11, in San Francisco

Think that DAC is all about EDA tools? Not anymore. This year there are over 100…

PaulaJones 22 May 2015 • 2 min read

controller IP , Verification IP , DSP , Design IP , IP , Chris Rowen , Rowen , IP blocks , ip cores , Tensilica , DAC 2015 , Design IP and Verification IP

SoC and IP

How to Design to the ‘Always-on’ IoT Imperative

I’ll never forget covering a presentation that then-National Semiconductor CEO Brian…

Brian Fuller 21 May 2015 • 2 min read

IP , Chris Rowen , cadence , IoT , Fusion , Tensilica , Internet of Everything. , Internet of Things

Analog/Custom Design

Virtuosity: 19 Things I Learned in April 2015 by Browsing Cadence Online Support

Application Notes 1. Spectre PSPICE Netlist Support Spectre technology enables…

stacyw 20 May 2015 • 5 min read

AMS , ADE XL , UNL , Monte Carlo , Virtuoso , Liberate , VLS XL , VCP

Whiteboard Wednesdays

Whiteboard Wednesdays—Type C Connector and USB Controllers

In this week's Whiteboard Wednesdays video, Jacek Duda explains the implications…

References4U 19 May 2015 • less than a min read

Whiteboard Wednesdays , controller , USB , Type C connector , On-the-go

System, PCB, & Package Design

What's Good About Allegro PCB Editor Split Plane Association? 16.6 Has Several New…

In the 16.6 Allegro PCB Editor release, net associations to split planes are now…

Jerry GenPart 19 May 2015 • 1 min read

PCB Layout and routing , Cadence Design Systems , Allegro 16.6 , PCB Editor , Layout , PCB design , Grzenia , Allegro PCB Editor , Allegro

Whiteboard Wednesdays

Whiteboard Wednesdays—Innovations in the DRAM World

In this week's Whiteboard Wednesdays video, Lou Ternullo reviews the latest DRAM…

References4U 12 May 2015 • less than a min read

Whiteboard Wednesdays , IP , DRAM , system level , density

Verification

Indago Protocol Debug and IP Verification

Nothing beats knowing, a late electronics-industry veteran used to say. That’s no…

Brian Fuller 7 May 2015 • 3 min read

IP , cadence , debug , Functional Verification , electronics system design , Indago , engineering , verification

Whiteboard Wednesdays

Whiteboard Wednesdays—Why Buy Memory Models?

In this week's Whiteboard Wednesdays video, Susan Peterson breaks down why you should…

References4U 5 May 2015 • less than a min read

Whiteboard Wednesdays , IP , memory models

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