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System, PCB, & Package Design

BGA Ball Map Creation

Are you responsible for the creation and management of a BGA ball map or a die bump…

TeamAllegro 6 Jul 2015 • 1 min read

Co-Design , IC package design , I/O planning , BGA ball map

Verification

Performance and the Use of Port mvl Lists (or, Nothing in Life is Free…)

When connecting to the DUT signals, we usually refer to the values as 0s or 1s. But…

teamspecman 2 Jul 2015 • 4 min read

performance , Specman , Functional Verification , Incisive , e , e language

System, PCB, & Package Design

Designing a Complex Leadframe Package? See How SiP Layout Tool Can Cover All the…

Leadframe package designs are here to stay, and they are getting more complex with…

ICPackagingPro 2 Jul 2015 • 7 min read

IC Packaging and SiP Design , Cadence Design Systems , leadframe , SiP , Digital SiP design , design variants , IC package design , package design , SiP Layout , wirebonding

Verification

The Dark Side of Constraints on 'do-not-generate' Fields

The art of expressing hardware functionality through constraint language is often…

teamspecman 30 Jun 2015 • 7 min read

IntelliGen , Specman , Functional Verification , e language , constraint coding

Verification

Debugging Multi-Language Verification Environments

As shown in previous blog posts in the Multi-Language Verification Environment series…

teamspecman 29 Jun 2015 • 4 min read

uvm , UVM-ML , multi-language verification , debugging

Digital Design

Five-Minute Tutorial: Innovus Placement Optimization

Hi Everyone, Last time we got a quick look at The Innovus Standard Flow . Now…

Kari 26 Jun 2015 • less than a min read

GigaPlace , Timing Optimization , Innovus , Placement

Whiteboard Wednesdays

Whiteboard Wednesdays—What Is PCI Express Address Translation Services?

In this week's Whiteboard Wednesdays video, Gopi Krishna defines and describes how…

References4U 23 Jun 2015 • less than a min read

Whiteboard Wednesdays , address translation services , PCIe , PCI Express

SoC and IP

Find Everything You Need to Build an Advanced PCI Express 4.0 Solution in One Booth…

The PCI-SIG Developers Conference happening today and tomorrow will be yet another…

Steve Brown 23 Jun 2015 • 2 min read

PCIe Gen4 , pcie gen2 , 16nm , PCIe Gen3 , PCI-SIG

Analog/Custom Design

Things You Didn't Know About Virtuoso: Help Us to Help You

There is a team at Cadence working on developing the next generation of Cadence documentation…

stacyw 19 Jun 2015 • less than a min read

Virtuoso , Cadence Help , online documentation , Cadence support

System, PCB, & Package Design

Manage All Design Variant Options for Your Package Substrate Seamlessly Using 16…

Stacked memory is becoming increasingly common in IC package substrates; with that…

ICPackagingPro 18 Jun 2015 • 2 min read

IC Packaging and SiP Design , stacked dies , SiP , IC Package , IC Packaging , SiP Design , design variants , package design , SiP Layout

SoC and IP

Sensor Processing, How Hard Can It Be?

When I think back back just a few years ago, there were only a handful of devices…

IPGuy 17 Jun 2015 • 2 min read

DSP , IP , IP blocks , controller , IoT , SoC , Fusion , ip cores , Processor IP , Tensilica , semiconductor IP , Internet of Things , Design IP and Verification IP , always-on