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SoC and IP

Cadence Firmware Packages Enable Successful IP Integration

Building a system on chip (SoC) from IP blocks requires system-level integration…

Cyprian Wronka 26 Jan 2015 • 3 min read

Bring-up , IP integration , ip cores , firmware

SoC and IP

Get a Glimpse at New Ethernet Standards in the Works

I attended the IEEE 802.3 meeting in Atlanta last week. I have blogged about Ethernet…

ArthurM 23 Jan 2015 • 2 min read

25G Ethernet , new Ethernet standards , Ethernet standards , Automotive Ethernet , IEEE 802.3 , ip cores , Ethernet

Verification

Dealing with the "Throw it Over the Wall" Methodology in Power Supply Network De…

"Throw it over the wall" is business slang for completing your part of a project…

BWinkeler 21 Jan 2015 • 2 min read

PSN , Power Supply Network , debug , Functional Verification , power-aware , UPF

Verification

Searching Through a Complex Design? DFS to the Rescue!

Recently, while at a customer site, I was faced with the huge task of looking for…

SwatiR 21 Jan 2015 • 4 min read

Functional Verification , simvision , design file search , Incisive Enterprise Simulator (IES)

Whiteboard Wednesdays

Whiteboard Wednesdays—Lower BOM Cost, Use 32-bit Wide LPDDR4 in Consumer Applica…

In this week's Whiteboard Wednesdays video, the second of a two-part series, Jeffrey…

References4U 20 Jan 2015 • less than a min read

Whiteboard Wednesdays , IP , LPDDR4 , 32-bit

SoC and IP

Cadence at CES 2015: Power-Sensitive Always-On Systems

LAS VEGAS—As the mobile world matures, opportunities abound for optimizing the user…

Brian Fuller 20 Jan 2015 • less than a min read

audio , power management , HiFi Mini , Tensilica , Realtek Semiconductor , HiFi DSP , CES 2015

Verification

Lazy Test Cases for Tool Failures Using the Testcase Optimizer (TCO)

The Current State It seems to be a fact of life that software has bugs and, unfortunately…

Uwe Simm 16 Jan 2015 • 7 min read

performance , methodology , verification strategy , debug , tech tips , Incisive , universal verification methodology , verification

SoC and IP

Cadence at CES 2015: A Look at Face-Detection Technology

LAS VEGAS—A key function of automotive, IoT, security, and similar applications is…

Brian Fuller 15 Jan 2015 • less than a min read

IP , cadence , IVP , Xtensa , CES 2015 , image processing , video processing

Whiteboard Wednesdays

Whiteboard Wednesdays—New LPDDR4 Standard Features

In this week's Whiteboard Wednesdays video, the first of a two-part series, Jeffrey…

References4U 13 Jan 2015 • less than a min read

Whiteboard Wednesdays , LPDDR4 , DBI , LVSTL

SoC and IP

Cadence at CES 2015: The IP Story

LAS VEGAS—The annual International Consumer Electronics Show (CES) here is not just…

Brian Fuller 12 Jan 2015 • less than a min read

ip cores semiconductor IP , EDA companies , Martin Lund , IP design , CES 2015

SoC and IP

My Top 10 List from CES

After nearly a week at CES, almost everyone is asking me – what was the big thing…

PaulaJones 12 Jan 2015 • 4 min read

DSP , Design IP , IP , CES , audio , video , IoT , HiFi , ip cores , Tensilica , semiconductor IP , Internet of Things , imaging

System, PCB, & Package Design

Customer Support Recommended—Modeling Voltage-Controlled Oscillators (VCO) Using…

A voltage-controlled oscillator (VCO) is an electronic oscillator whose oscillation…

Naveen 7 Jan 2015 • 2 min read

AMS , Allegro 16.6 , Allegro 16.5 , PSPICE , PCB design , SPB16.5

Whiteboard Wednesdays

Whiteboard Wednesdays—Soundwire Audio Interface

In this week's Whiteboard Wednesdays video, the first of a two-part series, Charles…

References4U 6 Jan 2015 • less than a min read

Whiteboard Wednesdays , IP , audio , MIPI , Soundwire

System, PCB, & Package Design

What's Good About OrCAD Capture’s Customization Capabilities? 16.6 has Several New…

The 16.6 release of OrCAD Capture/Capture-CIS provides several areas for you to customize…

Jerry GenPart 6 Jan 2015 • 2 min read

OrCAD Capture , 16.6 , Capture CIS , Grzenia , Schematic

Verification

Using Generative List Pseudo Methods in Constraints – A Case Study

This article highlights the use of list pseudo-methods constraining the content of…

teamspecman 6 Jan 2015 • 2 min read

Specman , list pseudo-methods , Ethernet , constraint coding , debugging

SoC and IP

Cadence at CES 2015: Experience Integrated Solutions for Mobile

Given that CES is a novelty-focused event, it is crucial that innovative companies…

Jacek Duda 20 Dec 2014 • 2 min read

Design IP , cadence , Consumer Electronics Show , CES , DIP , DSI , Tensilica , CES 2015 , MIPI D-PHY

Verification

Connected Field Sets – What Are Those and Why Should I Care?

Right form the start Specman has been very good at generating constrained random…

teamspecman 17 Dec 2014 • 4 min read

connected field sets , Specman , modeling constraints , IntelliGen constraint solver , Constraints , debugging

SoC and IP

Driven by Mobile, LPDDR4 Poised to Step Up

SANTA CLARA, Calif.—In the long and storied history of semiconductor memories, the…

Brian Fuller 16 Dec 2014 • 2 min read

IP , DDR4 , MemCon 2014 , IoT , IP integration , memory IP , ip cores , future of IP

Whiteboard Wednesdays

Whiteboard Wednesdays—SoC Interconnect Verification

In this week's Whiteboard Wednesdays video, Tom Hackett discusses the VIP Catalog…

References4U 16 Dec 2014 • less than a min read

Verification IP , Interconnect Workbench , Whiteboard Wednesdays , Interconnect Validator , VIP , verification

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