Cadence Community

Blog - Post List

Latest blogs

Verification

Updates from the UVM Multi-Language (ML) Front

An updated version of the UMV-ML Open Architecture library is now available on the…

teamspecman 15 Dec 2014 • 1 min read

funtional verification , SystemVerilog , UVM-ML , UVMWorld , UVM multi-language , e , SystemC

Analog/Custom Design

Top 5 Issues that Make Things Go Wrong in Mixed-Signal Verification

Key Findings : There are a host of issues that arise in mixed-signal verification…

TheLowRoad 10 Dec 2014 • 5 min read

MS , uvm , Metric-Driven-Verification , Palladium , Mixed Signal Verification , Incisive , MDV-UVM-MS , Virtuoso , mixed signal , MDV

Whiteboard Wednesdays

Whiteboard Wednesdays—Addressing the Advantages of Embedded LTE and Advanced LTE

In this week's Whiteboard Wednesdays video, Bob Salem discusses the advantages of…

References4U 9 Dec 2014 • less than a min read

Whiteboard Wednesdays , IP , SoC , mobile , LTE

Verification

Code Coverage at the System Level with Hardware-Assisted Verification? Are You Kidding…

Short answer: Nope, not kidding. You can get value from applying code coverage with…

rmathur 9 Dec 2014 • 2 min read

hardware-assisted verification , code coverage , functional coverage , verification closure , verification

System, PCB, & Package Design

What's Good About Allegro PCB Editor Vertically Placed Components? It’s in the 16…

The ‘dual_sided_component’ property in the Allegro PCB Editor 16.6 release can be…

Jerry GenPart 8 Dec 2014 • 1 min read

embedded components , interconnects , Allegro 16.6 , PCB design , Allegro PCB Editor

Verification

Dealing with Specman-Simulator Interface Issues—Get Ready to Cook!

Two great documents, aiming to make life easier for a verification engineer, were…

teamspecman 8 Dec 2014 • less than a min read

Specman , debug , Functional Verification , Incisive , e language , simulation

Verification

Time to Play - You Can Now Run Your e Code on EDAplayground

Over the years I've often hoped to have the ability to show someone (a customer,…

hannes 5 Dec 2014 • less than a min read

IEEE 1647 , Functional Verification , tech tips , EDA , e language , team specman , Aspect Oriented Programming

SoC and IP

USB Power Delivery Is Better with Type-C

In my previous blog post , I wrote how much better than the existing Type-A and Type…

Jacek Duda 5 Dec 2014 • 2 min read

USB 3.0 , Design IP , USB-IF , USB , power delivery , USB 2.0 , Type-C , USB connector , USB 3.1

Verification

Code Coverage at the System Level with Hardware-Assisted Verification (Part II)

In yesterday’s Part I blog post , I talked about a technique for focusing code coverage…

rmathur 3 Dec 2014 • 4 min read

hardware-assisted verification , code coverage , system-level code coverage , coverage analysis , functional coverage

Analog/Custom Design

Five Reasons I'm Excited About Mixed-Signal Verification in 2015

Key Findings : Many more design teams will be reaching the mixed-signal methodology…

TheLowRoad 3 Dec 2014 • 7 min read

uvm , mixed signal design , Metric-Driven-Verification , Mixed Signal Verification , MDV-UVM-MS

Whiteboard Wednesdays

Whiteboard Wednesdays—Consumer DRAM Trends

In this week's Whiteboard Wednesdays video, Lou Ternullo explains the DRAM trends…

References4U 2 Dec 2014 • less than a min read

Whiteboard Wednesdays , DDR4 , DRAM , DDR3

Whiteboard Wednesdays

Whiteboard Wednesdays—Selecting the Right DDR PHY Solution

In this week's Whiteboard Wednesdays video, Kishore Kasamsetty reviews evaluation…

References4U 20 Nov 2014 • less than a min read

Whiteboard Wednesdays , IP , Floorplanning , PHY IP , DFI

Analog/Custom Design

Mixing It Up in Hardware (an Advantest Case Study in Faster Full-Chip Simulations…

Key Findings: Advantest, in mixed-signal SoC design, sees 50X speedup, 25 day test…

TheLowRoad 19 Nov 2014 • 9 min read

Advantest , Palladium , Mixed Signal Verification , Emulation , mixed signal

System, PCB, & Package Design

What's Good About Allegro PCB Editor Select by Lasso or Path? 16.6 Has It!

The 16.6 Allegro PCB Editor release contains two new selection options, lasso and…

Jerry GenPart 18 Nov 2014 • 1 min read

PCB , PCB Layout and routing , Allegro GUI , Allegro 16.6 , cadence , Routing , route quality , bulk editing , SPB , PCB Editor , PCB design , Allegro PCB Editor

Whiteboard Wednesdays

Whiteboard Wednesdays—TripleCheck VIP

In this week's Whiteboard Wednesdays video, Moshik Ruben discusses TripleCheck verification…

References4U 11 Nov 2014 • less than a min read

Verification IP , Whiteboard Wednesdays , IP , VIP , TripleCheck

System, PCB, & Package Design

Multi-Fabric Planning for Efficient PCB Design

Recently, an article was published in Printed Circuit Design and Fab about Multi…

TeamAllegro 11 Nov 2014 • 1 min read

BGA-style package , PCB design , multi-fabric planning , pin assignment

Analog/Custom Design

Virtuosity: A Very Large Number of Things I Learned in September and October 2014…

There has been a flurry of activity on COS over that past couple of months. I can…

stacyw 10 Nov 2014 • 8 min read

AMS , MMSIM , Advanced Node , ADE XL , Virtuoso , Analog Design Environment , Custom IC Design , Virtuoso Layout Suite XL , IC 6.1.6

Verification

Where Is the Money for IoT?

I attended the Gartner Semiconductor briefing on Oct. 23, 2014, the theme of which…

Seow Yin Lim 10 Nov 2014 • 1 min read

Verification IP , DSP , IP , IoT , Tensilica , always-on

System, PCB, & Package Design

Do You Design Wafer-Level Chip-Scale Packages? Cadence 16.6 SiP Layout Makes Your…

As these types of designs see an increasing number of applications and design starts…

Jeff Gallagher 6 Nov 2014 • 4 min read

IC Package , SiP Design , Co-Design , layout pin numbering

Cadence Blogs

Category

Regional

Archive