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Analog/Custom Design

The Elephant in the Room: Mixed-Signal Models

Key Findings: Nearly 100% of SoCs are mixed-signal to some extent. Every one of these…

TheLowRoad 5 Nov 2014 • 5 min read

metrics-driven methodology , real number modeling , uvm , CPF , RNM , UPF , mixed signal , MDV , verification

Whiteboard Wednesdays

Whiteboard Wednesdays—Verification IP Productivity Tools

In this week's Whiteboard Wednesdays video, Tom Hackett talks about Cadence Verification…

References4U 4 Nov 2014 • less than a min read

Verification IP , Whiteboard Wednesdays , VIP , PureView , productivity , TripleCheck

SoC and IP

Its Name is C, Type-C: The New Superhero of Cables from USB

Isn’t it interesting how, with time, all the nitty-gritty of technology is starting…

Jacek Duda 4 Nov 2014 • 2 min read

Design IP , IP , Jacek Duda , USB , ip cores , USB3.0

Verification

Generic Dynamic Runtime Operations With e Reflection - Part 3: Additional Capabilities…

This post concludes the series of blog posts that discuss the dynamic capabilities…

teamspecman 3 Nov 2014 • 3 min read

AF , Specman , debug , Functional Verification , Incisive , e language , reflection , simulation

Verification

Transferring e "when" Subtypes to UVM SV via TLM Ports—UVM-ML OA Package

The UVM-ML OA (Universal Verification Methodology - Multi-Language - Open Architecture…

teamspecman 3 Nov 2014 • 5 min read

AF , uvm , Specman , debug , Functional Verification , Incisive , UVM ML , e language , simulation

Verification

Generic dynamic run-time operations with e reflection Part II

Field access and method invocations In the previous blog , we explained what are…

teamspecman 30 Oct 2014 • 4 min read

AF , Functiional Verification , e language , Funcional Verification , coverage driven verification (CDV) , Aspect Oriented Programming , reflection

Analog/Custom Design

It’s Late, But the Party is Just Getting Started

Key Findings: Many more chip programs are crossing the tipping point and need advanced…

TheLowRoad 30 Oct 2014 • 6 min read

AMS , analog behavior , AMS-Designer , AMS Designer , analog behavioral models , analog/mixed-signal , AMS Verification

SoC and IP

Call for Papers Now Open – CDNLive Silicon Valley

CDNLive Silicon Valley (March 10-11, 2015, Santa Clara Convention Center) provides…

PaulaJones 29 Oct 2014 • less than a min read

IP , EDA conference , CDNLive , IP papers , EDA papers

Whiteboard Wednesdays

Whiteboard Wednesdays—PCIe Controller Solution

In this week's Whiteboard Wednesdays video, Sandeep Brahmadathan breaks down Cadence…

References4U 28 Oct 2014 • less than a min read

performance , Whiteboard Wednesdays , PCIe , latency , PCI Express

System, PCB, & Package Design

What's Good About Using Sigrity and Cadence SiP Digital to Reduce Design Costs? Check…

This week, you can view a couple of videos where customers describe how they used…

Jerry GenPart 28 Oct 2014 • 1 min read

SiP , Digital SiP design , Power Integrity , Layout , Signal Integrity , PCB design , Sigrity

Whiteboard Wednesdays

Whiteboard Wednesdays—Configurable 10/40G Ethernet Solution

In this week's Whiteboard Wednesdays video, Arthur Marris discusses configurable…

References4U 21 Oct 2014 • less than a min read

Whiteboard Wednesdays , IP , Mac , 10/40G , Ethernet , SerDes , PCS

System, PCB, & Package Design

What's Good About Allegro PCB Editor Artwork Film Capabilities? 16.6 Has Several…

The 16.6 Allegro PCB Editor release contains several enhancement to the Artwork Film…

Jerry GenPart 21 Oct 2014 • 1 min read

PCB , PCB Layout and routing , Allegro GUI , Allegro 16.6 , artwork , SPB , PCB Editor , Layout , design , PCB design , Allegro PCB Editor , Allegro

Digital Design

Five-Minute Tutorial: One More Look at EM Models

Just when you thought you were done setting up EM model files, along came another…

Kari 20 Oct 2014 • 2 min read

Voltus , Digital Implementation , Power Analysis , EM , five minute tutorial

Whiteboard Wednesdays

Whiteboard Wednesdays—DDR Training Modes

In this week's Whiteboard Wednesdays video, Jeffrey Chung discusses the various training…

References4U 14 Oct 2014 • less than a min read

Whiteboard Wednesdays , training , DDR , timing

System, PCB, & Package Design

What's Good About Allegro PCB Editor New Slide Capabilities? 16.6 has Several New…

The 16.6 Allegro PCB Editor release's new ‘Slide’ command utilizes a move-intersect…

Jerry GenPart 8 Oct 2014 • 8 min read

PCB , PCB Layout and routing , interconnects , Allegro GUI , Allegro 16.6 , cadence , Routing , DRC , Placement Edit , diff pair , SPB , PCB Editor , High-Density Interconnect , Layout , Allegro router , PCB design , Spacing , Allegro PCB Editor

Whiteboard Wednesdays

Whiteboard Wednesdays—Choosing the Right NAND Flash Solution

In this week's Whiteboard Wednesdays video, Lou Ternullo walks you through the steps…

References4U 7 Oct 2014 • less than a min read

Whiteboard Wednesdays , IP , NAND flash

Verification

Looking Back at a Great Week for System Design!

Reflecting on last week at ARM TechCon, together with our close partner ARM, we had…

fschirrmeister 5 Oct 2014 • 3 min read

debug , System Design and Verification , embedded software , hybrid , ARM TechCon 2014 , ARM , verification

Verification

Cadence Palladium Platform and ARM Fast Models - Making the Future the Present

In its 10th year now, ARM TechCon is in full swing this week at the Santa Clara Convention…

fschirrmeister 2 Oct 2014 • 3 min read

NVIDIA , Palladium , hybrid , Emulation , ARM Fast Models , ARM

Whiteboard Wednesdays

Whiteboard Wednesdays—Ethernet in Cars

In this week's Whiteboard Wednesdays, Arthur Marris introduces the next big thing…

References4U 30 Sep 2014 • less than a min read

communication protocol , Automotive Ethernet , Ethernet , open standard , interoperability

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