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Digital Design

Cadence Welcomes Ausdia and TimeVision Timing Constraints Management Solution

We're delighted to welcome Ausdia to Cadence. Effective April 16, 2026, Ausdia's…

Corporate
• 2 min read
digital design , Digital Design and Signoff , featured , Tempus timing solution , Timing analysis

Corporate News

The Rise of the Autonomous Engineer

Agentic AI in engineering has moved from concept to reality at remarkable speed.…

Corporate
• 5 min read
featured , agentic ai , NVIDIA , AI-Driven Design , AI for design

Corporate News

Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered…

Corporate
• 4 min read
CMOS 2.0 , featured , imec , AI for design , XTCO

Corporate News

Welcoming EMA Design Automation and FlowCAD to Cadence

We're excited to share that the EMA Design Automation and FlowCAD teams have joined…

Corporate
• 2 min read
featured , Ultra Librarian , EMA , System Design and Analysis
cdns - all_blogs_categories

Blog - Post List
Latest blogs

System, PCB, & Package Design 

What's Good About DEHDL “How To” Videos? The Secret's in the 16.6 Release!

While there are several videos available for Allegro Design Entry HDL (DEHDL) in…

• 1 min read
PCB , Allegro Design Entry , Allegro 16.6 , PCB design videos , electrical constraints , flat schematics , hierarchical schematics , Allegro 16.5 , SPB , Design Entry HDL , Design Entry , ConceptHDL

Analog/Custom Design

Efficient Design Migration Using Virtuoso Analog Design Environment GXL

Requirements for decreased time to market, reduced silicon area, and minimized power…

• 2 min read
Analog Design Environment , ADE GXL , ADE XL , Virtuoso , Custom IC Design , Design Migration

System, PCB, & Package Design 

What's Good About ADW’s Board File Management? 16.6 Has a Few New Enhancements!

There are two new use models for PCB designers using Allegro Design Workbench (ADW…

• 1 min read
PCB , PCB Layout and routing , Allegro 16.6 , Allegro Design Workbench , PCB Editor , design data management , design , PCB design , Allegro PCB Editor , ADW

Whiteboard Wednesdays

Whiteboard Wednesdays - Why Cadence Verification IP (VIP) is a Smart Choice for …

In this week's Whiteboard Wednesdays episode, Tom Hackett discusses why over 500…

• less than a min read
Verification IP , Whiteboard Wednesdays , IP , SoC design , verifying SoCs

Verification

Cadence Announces Verification IP for MIPI SoundWire and C-PHY

Anyone who has been involved in designing mobile devices in recent years is familiar…

• less than a min read
Verification IP , MIPI Alliance , cadence , audio , PureSpec , Slimbus , VIP , MIPI , CSI , M-PCIe , Denali , C-PHY , Soundwire , M-PHY

Whiteboard Wednesdays

Whiteboard Wednesdays - New MIPI Interfaces: Winners or Losers?

In this week's Whiteboard Wednesdays installment, Cadence's Moshik Ruben takes a…

• less than a min read
Whiteboard Wednesdays , M-PCIe , MIPI protocols , USB , mobile interfaces , mobile

Verification

The Importance of Ecosystems in the Internet of Things Era

As we develop electronics in early 2014, the battle between processor architectures…

• 4 min read
ARM ecosystem , System Design and Verification , electronics design , Internet of Things , ARM , embedded systems

Analog/Custom Design

Fast Yield Analysis and Statistical Corners

The Virtuoso Analog Design Environment XL Monte Carlo sampling methods are Random…

• 3 min read
ADE GXL , ADE XL , fast yield analysis , Virtuoso Analog Design Environment , Monte Carlo , statistical corners

Verification

Randomizing Error Locations in a 2D Array

A design team at a customer of mine started out with Specman for the first time…

• 3 min read
AF , IntelliGen , Specman , e code , stimuli , Generation , Funcional Verification

SoC and IP

RealTek Shows New HiFi-based Codec with Software from Sensory and ForteMedia

Watch these demonstrations of RealTek's new ALC5677 audio codec - which uses HiFi…

• less than a min read
voice recognition , audio , Sensory , microphone , HiFi , Tensilica , ForteMedia , always-on , RealTek

Analog/Custom Design

Virtuosity: 14 Things I Learned in January and February 2014 by Browsing Cadence…

Time just got away from me last month, so here's two months worth of new content…

• 2 min read
AMS , Corners , ADE , ADE-GXL , PVT corners , Custom IC Design , Virtuoso Layout Suite

System, PCB, & Package Design 

Customize Your Menus Dynamically with SKILL in Cadence Allegro 16.6-Based Layout…

Many users of the Allegro, APD, and SiP tools are familiar with the great flexibility…

• 5 min read
IC Packaging and SiP Design , IC packaging SiP Layout , Digital SiP design , IC Packaging & SiP design , IC packaging documentation , IC Package Physical layout and co-design

Whiteboard Wednesdays

Whiteboard Wednesdays—How 2D Solutions Help Close the Memory Wall Gap

In this week's Whiteboard Wednesdays episode, Scott Jacobson deep dives into 2D memory…

• less than a min read
performance , Whiteboard Wednesdays , 2D Memory , DDR4 , UFS , eMMC , power

SoC and IP

MIPI Protocols—Making Mobile Happen at MWC

MIPI protocols are expected to ship in over 4 billion mobile devices this year. That…

• less than a min read
controller IP , Verification IP , Design IP , IP , MIPI Alliance , PHY , BIF , Slimbus , VIP , MIPI , CSI , MWC , semiconductor IP , M-PHY

SoC and IP

Android Audio Offload Explained at Mobile World Congress

Want to lower power in your next Android TM device? Look to the industry's first…

• less than a min read

Verification

New Incisive Verification App and Papers at DVCon by Marvell and TI

If you're an avid reader of Cadence press releases (and what self-respecting verification…

• 1 min read
Formal Analysis , formal , Funcional Verification , DVCon 2014 , Formal verification , Assertion-based verification

System, PCB, & Package Design 

What's Good About DEHDL’s Cross Referencing of Hierarchical Nets? 16.6 has Several…

The 16.6 Design Entry HDL (DEHDL) Cross Referencer has some new enhancements to report…

• less than a min read
PCB , Cadence Design Systems , hierarchy , cadence , 16.6 , hierarchical schematics , SPB , Design Entry HDL , design , Design Entry , Grzenia , ConceptHDL , hierarchical block

Verification

Incisive vManager at DVCon - Come See It!

Have you heard the news? There is a new version of vManager announced this week,…

• 1 min read
collaboration , : Functional Verification , Verification methodology , cadence , Functional Verification , vPlan , Verisity , DVcon , metric-driven verification , functional coverage , vManager

Whiteboard Wednesdays

Whiteboard Wednesdays - How the MIPI Alliance Works to Enhance Mobile Devices

In this week's Whiteboard Wednesdays episode, Moshik Ruben, Product Marketing Director…

• less than a min read
mobile devices , UniPro , D-PHY , MIPI , MIPI protocols , M-PHY
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