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Himax Accelerates Chip Design with Cadence Cerebrus Intelligent Chip Explorer

Himax Technologies Inc ., a leading supplier and fabless manufacturer of display…

Vinod Khera
• 2 min read
featured , Cadence Cerebrus Intelligent Chip Explorer , Digital Implementation , AI/ML

Transforming Chip Design with Cadence Cerebrus AI Studio

Cadence is transforming chip design with the launch of Cadence Cerebrus ® AI Studio…

Sean Kobayashi
• 1 min read
digital design , featured , agentic ai , designed with cadence , Cadence Cerebrus

Conformal AI Studio: Accelerated LEC/ECO/LP with AI/ML-Driven Enhancements

If you're a chip designer or verification engineer, you have likely spent countless…

David Stratman
• 5 min read
conformal , featured , Digital Implementation , Conformal AI Studio , AI/ML
Digital Design

Latest blogs

Voltus Voice: Voltus-Sigrity Collaboration Fuels System Innovation

Learn how the Voltus-Sigrity X integrated solution can help you achieve faster system…

• 3 min read
Voltus IC Power Integrity Solution , Power Signoff , 3D-IC , Signoff Analysis , Power Integrity

How Does Marvell Improve Productivity and TapeOut Time with Automated ECO Implementation…

How to fix the bugs after RTL freeze and perform ECO. Learn how Automated ECO Implementation…

• 3 min read
ECO , Conformal ECO Designer

Training Insights – Webinar – Transforming your Timing Signoff Experience with Tempus…

This webinar encourages you to learn and apply the latest innovations in the Cadence…

• 3 min read
Static timing analysis , Silicon Signoff and Verification , Digital Implementation , Tempus Timing Signoff Solution

HLS for AI/ML Models: TensorFlow to RTL

Artificial Intelligence (AI) plays a key role in semiconductors to meet the challenging…

• 3 min read
Stratus HLS , Genus

Voltus Voice: How to Find Functional Power Vectors that Matter Quickly

Vector profiling enables ASIC designers to quickly identify areas with maximum activity…

• 6 min read
switching power , Low Power , Voltus IC Power Integrity Solution , power consumption , Power Signoff , Power Profile , Digital Implementation , switching activity , Power Analysis , vector profiling

Relax in Summer with Cooler IC chips and Ice-Cream! Do you want to Explore the Recipe…

Are you passionate about cooking? Err... Don't think it is a regular cooking class…

• 1 min read
Low Power , Genus , IEEE 1801 , UPF , Synthesis

Resolve Congestion and Physical Design Challenges Using Cadence Support and RAKs

Physical design challenges such as congestion, routing, on-chip variation (OCV),…

• 5 min read
routing congestion , OCV , clock tree synthesis , Innovus , Rapid Adoption Kits , Cadence support

Voltus Voice: Five Great Features to Enhance Your Full-Chip Power Signoff

This blog shares five great features to unlock the potential of your digital designs…

• 5 min read
Celsius Thermal Solver , scan chain , featured , power density , Voltus IC Power Integrity Solution , Power Signoff , Signoff Analysis , Power Integrity , learning , Power-Efficient Design , noise analysis , vector-based , Thermal Analysis , Power Analysis , vector profiling , vectorless , dynamic power

SSV 22.1 Base Release Now Available

The Silicon Signoff and Verification (SSV) 22.1 release is now available for download

• 3 min read
Cadence blogs , Voltus IC Power Integrity Solution , 3D-IC , Power Integrity , multi-die design , Timing analysis , Power Analysis , Aging-Aware STA , silicon signoff , Tempus Timing Signoff Solution

Training Insights – Design Robustness Analysis Application: Aging-Aware STA

This blog post describes the phenomenon of Aging, the factors affecting it, and how…

• 2 min read
Timing analysis , aging , Liberate , silicon signoff , Tempus Timing Signoff Solution

Brain on Fire - AI/ML Art Creation

No matter how you feel about the topic, we're definitely past the turning point in…

FormerMember • 1 min read
Silicon Signoff and Verification , Genus , Tempus , cerebrus , Digital Implementation , Innovus

RTL-to-GDSII Flow: I Am Not a Tool but Can Help You Implement Your Entire Design…

Passion motivates and helps you pursue it further, but gaining expertise requires…

• 4 min read
ECO , conformal , Static timing analysis , VLSI , scan , DFT , Integrated Metrics Center , Genus , featured , Cadence blogs , GDSII , code coverage , Tempus , Functional Verification , Gate level simualtion , ASIC flow , gds , LEC , Signoff Analysis , RTL , SDF , STA , Cadence Online Support , Floorplanning , RTL-to-GDSII , training , Logic Design , xrun , Equivalence Checking , Layout , digital flow , Digital Implementation , Innovus , physical design , Timing analysis , Cadence Education Services , ATPG , xcelium , RTL2GDSII , Synthesis , signoff , physical implementation , Design specifications , verification , cadence learning and support

What's Behind the 5% Die-Area Shrink and 12% Power Saving by MediaTek?

Leveraging Cadence Cerberus AI-Enabled Chip Optimization Solution MediaTek Achieves…

• 3 min read
Intelligent chip explorer , featured , Cadence Cerebrus , Digital Implementation , AI

Training Insights - Achieving a Holistic Power-Aware Design by Getting Low-Power…

This blog post mentions the Cadence Low Power Solution, a design-to-signoff methodology…

• 2 min read
Low Power , digital implementation , Innovus

Voltus Voice: Overcoming Design Challenges Using Voltus Documentation—The Definitive…

This post facilitates easy access to the Voltus Help and Documentation through the…

• 3 min read
digital badge , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , training bytes , Digital Implementation , Cadence Education Services

Scan Mapping, Expectation Versus Reality? It's Time to Grab All the Scan Cells!

We all look for 100% perfection and want to turn our dreams (expectations) into reality…

• 1 min read
scan , DFT , Genus , Synthesis

Power Is HOT and Touches Everything and Everybody! But the Challenge Is To Deal With…

Low-Power synthesis is one of the important stages in the full IC flow. Here, you…

• less than a min read
Low Power , Genus , Digital Implementation , Synthesis , power optimization

Are You Planning To Synthesize Your Design? Do You Want To Explore the Synthesis…

A Logic Synthesis is a process of optimizing the design's area, timing, and power…

• less than a min read
Genus , Flows , Logic Design , Optimize , Synthesis

Chris, Kris, Cris, Your Name, My Name; Does How You Spell the Name Matter to Conformal…

No matter how your name is spelt in different countries, and how they say it, once…

FormerMember • 1 min read
digital badge , conformal , training bytes , online training

Do You Want to Explore Instances in Genus Synthesis Solution Layout GUI?

What comes to your mind when we say Genus Layout GUI (Graphical User Interface)?…

• less than a min read
Genus , gui , place and route , highlighted objects , physical implementation

Voltus Voice: Simplifying Power Signoff for HPC Systems: Super-Charge your Power…

In the first post of our " Simplifying Power Signoff for HPC Systems" blog series…

• 4 min read
Silicon Signoff and Verification , Voltus IC Power Integrity Solution , Power Signoff , Cycle Accurate Power Estimation , Event-Based Power Analysis , Power Analysis

Floorplanning Frustrations Got You Down? Help Is on the Way!

This post describes a channel of videos created to show how to floorplan a design…

• less than a min read
Floorplanning , Innovus

Mitigating Congestion, CTS, OCV and Other Challenges using Cadence Tools and Sup…

With the shrinking gemoetries and data-intensive endeavours of the upcoming industries…

• 6 min read
debug , Routing , Unconstrained Path , congestion , OCV , SOCV , RAKs

Voltus Voice: Early Power and Thermal Integrity Analysis in 3D-ICs - Why it Really…

Learn how to navigate through the challenges of power and thermal integrity analysis…

• 2 min read
Celsius Thermal Solver , system in package , Voltus IC Power Integrity Solution , Integrity 3D-IC Platform , 3D-IC , Power Integrity , Thermal Integrity , Multi-Chiplet Design

Voltus Voice: Hierarchical Power Integrity Analysis—Why xPGV Modeling Is the Designer…

In the final part of our "Hierarchical Power Integrity Analysis" blog series, we…

• 4 min read
Voltus XM , Silicon Signoff and Verification , Voltus IC Power Integrity Solution , xPGV models , Power Integrity , hierarchical power integrity analysis , IRdrop , Extreme Modeling , Full-Chip

Adopting a Faster, More Efficient Path to Multi-Chiplet Design

Gone are the days when process shrinking was considered as the primary driver of…

• 3 min read
chiplets , 3D-IC , Integrity , Thermal Integrity , system planning , Multi-Chiplet Design

Is your Compression Technique Unified? Wanna Explore?

Scan compression is critical for addressing the rapid rise of test costs without…

• 1 min read
scan , DFT , compression , Genus , Synthesis

Voltus Voice: Playback 2021 - Power Integrity Blogs At a Glance

A recap of the power integrity posts in the Voltus Voice blog series through 2021…

• 3 min read
Silicon Signoff and Verification , Voltus IC Power Integrity Solution , electrostatic discharge , resistance analysis , hierarchical power integrity analysis , Digital Implementation , rush current analysis
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