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Latest Blog Posts

  • 定制IC芯片设计 : Virtuosity: 我的 Checks 通过还是没有运行?

    AdityaMainkar
    AdityaMainkar
    今天的博客重点介绍 Checks/Asserts 结果显示和 Summary 表。 这个博客是我们每周发布两次 - 周二和周四 - 的迷你博客系列的一部分,以涵盖 Virtuoso®ADE Assembler,Virtuoso®ADE Explorer 和 Virtuoso® Visualization and Analysis中刚刚发布的功能。 请继续关注更多此类有趣的博客。 如果您曾尝试在 Virtuoso® ADE Assembler 和&...
    • 22 Jul 2019
  • Analog/Custom Design: Tales from DAC: MediaTek's Experience with Spectre X Simulator

    XTeam
    XTeam

    MediaTek recently gave the new Spectre X Simulator a try, and they talked about their experiences with it at DAC 2019 in a presentation given by YY Chen in the Cadence Theater.

    Spoiler alert: they loved it.

    MediaTek is the fourth largest fabless IC design company in the world, and they’re ranked #1 in the voice assistant device, android tablet, and network connectivity markets, among others. They, like so many others…

    • 22 Jul 2019
  • System, PCB, & Package Design : DATA Pulse: In Search of the Perfect Environment—Configuring Allegro EDM

    Auromala
    Auromala

      Ah, the office temperature – that eternal debate. As in many offices, ours has some people who feel that they're in the Sahara Desert, others who bundle up like they're in Antarctica, a few who just don't care about the temperature, and some who can't quite figure out if they're ever comfortable, like Goldilocks. There is however no 'perfect' temperature. So many variables impact the physical environment of the office…

    • 22 Jul 2019
  • Analog/Custom Design: Virtuoso Meets Maxwell: Export the Die? What Am I Exporting? To Where?

    kgjudd
    kgjudd
    Here I come back with another episode of TILP of the Virtuoso Meets Maxwell series! In my earlier post "TILP! What's A TILP?", I introduced the concept of Technology Independent Layout Pcell (TILP). Today we are going to create a TILP, which is used in the package design, from a die.
    • 22 Jul 2019
  • Breakfast Bytes: Passwords and Multi-Factor Authentication

    Paul McLellan
    Paul McLellan
    I recently came across an interesting piece written by Microsoft's Alex Weinert, Your Pa$$word doesn't matter. He is part of Microsoft's Security and Protection Team. As such he is involved in keeping Microsoft's Azure Cloud solu...
    • 22 Jul 2019
  • Breakfast Bytes: Sunday Brunch Video for 21st July 2019

    Paul McLellan
    Paul McLellan
    https://youtu.be/JHWXXezFMU8 Made at Krakow, Poland (camera Gary Bengier) Monday: Will American Scooters Follow Chinese Bikes? Tuesday: GLOBALFOUNDRIES After the Pivot Wednesday: Intelligent System Design for Automobiles of the Future Thursday: ...
    • 21 Jul 2019
  • Breakfast Bytes: The First Computer on the Moon

    Paul McLellan
    Paul McLellan
    I am sure you can't fail to have noticed that tomorrow is the 50th anniversary of the first landing on the moon. It has been everywhere for the last few weeks. I was a teenager. I remember watching the landing. In Britain, in the basement at my p...
    • 19 Jul 2019
  • PCB、IC封装:设计与仿真分析: 关于PCB安装孔所需了解的一切

    TeamAllegro
    TeamAllegro
    安装孔似乎很简单——只需将印刷电路板安装到外壳或表面上,选择一个适合电路板以及待安装表面的螺丝尺寸,然后根据此规格钻孔即可。 但与印刷电路板中其他设计一样,当增加高速信号并减小形状因子后,安装孔将变得复杂起来。突然间,每个导电层都能影响电磁干扰覆盖区域,包括安装孔。这时,我们就需要考虑公差,从而确保为电路板上所需的所有元件、过孔和走线留足间隙。 那么,除了目视要求,安装孔设计还应该注意哪些方面呢? 安装孔配置 安装孔通常可分为两类: 带有支撑特性:通常连接接地平面的电镀...
    • 18 Jul 2019
  • Analog/Custom Design: Virtuosity: Introducing Automated Device Placement and Routing in Virtuoso

    Sravasti
    Sravasti
    This blog provides an overview of the fully automated device-level placement and routing solution, which is available at advanced nodes.
    • 18 Jul 2019
  • Verification: Tales from DAC: Cadence, AI, and You

    XTeam
    XTeam

    Complexity is driving the urgency for advanced artificial intelligence systems more than ever—and that means someone has to supply the tools to create those systems. Cadence is up to the task: we’ve been expanding our AI offerings. If you haven’t already seen what Cadence can do for your AI needs, or if you’re not quite up-to-date on this whole AI boom, let this presentation given by K.T. Moore…

    • 18 Jul 2019
  • 定制IC芯片设计 : Virtuosity: 模拟设计环境中的最重要的3个后仿改进功能

    Arja H
    Arja H
    今天的博客重点介绍了后仿流程的最新增强功能。 这些增强功能解决了许多长期存在的问题,例如原理图和版图命名的匹配,绘制端口电压和DSPF文件扫描。 这个博客是我们每周发布两次 - 周二和周四 - 的迷你博客系列的一部分,以涵盖Virtuoso®ADE Assembler,Virtuoso® ADE Explorer和Virtuoso® Visualization and Analysis中刚刚发布的功能。 请继续关注更多此类有趣的博客。 你有没有想过扫描不同Corne...
    • 18 Jul 2019
  • Breakfast Bytes: Orchestras, Degrees, and Choice

    Paul McLellan
    Paul McLellan
    Did you read about how orchestras started to do blind auditions where the players were behind a curtain? And how the result was lots more women hired into orchestras once the biased hiring committees couldn’t act on their prejudices…wome...
    • 18 Jul 2019
  • Analog/Custom Design: Tales from DAC: The New Spectre Simulator Is Here!

    XTeam
    XTeam

    If you’re doing circuit simulation anywhere in the world, you’re probably already familiar with the Cadence Spectre® simulator. The Spectre simulator is an accurate and high-performance SPICE circuit simulator that has established itself as the golden reference analog simulation over many years of use by designers. Now, with smaller geometries and denser chip designs, requiring more performance and capacity, the Spectre…

    • 17 Jul 2019
  • Breakfast Bytes: Intelligent System Design for Automobiles of the Future

    Paul McLellan
    Paul McLellan
    There's a lot going on in the automotive market. The three big things are electric traction, autonomous driving, and shared mobility. Cadence is holding their second annual Automotive Design Summit on July 30 in San Jose, where all aspects of aut...
    • 17 Jul 2019
  • System, PCB, & Package Design : BoardSurfers: Avoid Iterations with Your Manufacturing Partner – Detect and Address DFM Issues in the Design Phase Using DesignTrue DFM

    mrigashira
    mrigashira

     Some things are rare, good or bad, but they do happen from time to time. And, some happen so regularly, we often take them for granted if good or learn to live with them if bad. But should we? For example, you send out your design for fabrication and the CAM (computer-aided manufacturing) engineer runs a high-end design for manufacturability (DFM) analysis software. The CAM engineer sees DFM issues (almost always!). Now…

    • 16 Jul 2019
  • Whiteboard Wednesdays: Whiteboard Wednesdays – What is Happening at the USB IF Standards Meetings?

    References4U
    References4U

    In this week’s Whiteboard Wednesdays video, Jacek Duda talks about the next-generation standard, USB4.  What are the benefits? Overlap with existing USB standards? How does it compare with USB 3.x? Watch the video.

    https://youtu.be/sKHF8xB-NBk

    • 16 Jul 2019
  • System, PCB, & Package Design : IC Packagers: Bend in Both Directions with J-Loop Bond Wires

    Tyler
    Tyler
    Let’s talk about wire bonding for a quick minute. Still a favorite for many of you, bonding is a cheap way to connect your die to the top layer of your package (or to a lead frame, if that’s what you’re using). A 3D wire is connecte...
    • 16 Jul 2019
  • Breakfast Bytes: GLOBALFOUNDRIES After the Pivot

    Paul McLellan
    Paul McLellan
    At SEMICON West I sat down with Gary Patton, CTO of GLOBALFOUNDRIES, to get an update on what is going on since the “pivot”. The Pivot The pivot was the decision last year to pull back from 7nm and EUV development and focus their process ...
    • 16 Jul 2019
  • 定制IC芯片设计 : Virtuoso 视频日记: Reliability Setup 的新功能

    Udit Rajput
    Udit Rajput
    今天的博客重点介绍了可 reliability options 表单和整体 reliability setup 的增强功能。这个博客是我们迷你博客系列的一部分。我们会在每周二,周四各发布一次。我们的博客会涵盖 Virtuoso® ADE Assembler, Virtuoso® ADE Explorer 和 Virtuoso® Visualization and Analysis 中刚刚发布的功能。请继续关注更多此类有趣的博客。. 您是否曾使用 Rel...
    • 16 Jul 2019
  • Life at Cadence: Cadence and the Expanding Presence of Women in Tech Conferences

    FormerMember
    FormerMember
    Cadence sponsors several different tech conferences throughout the year. We use these events as an opportunity to allow employees to take a day out of our normal work routine to network, learn, and develop as leaders—but more importantly, so we...
    • 15 Jul 2019
  • SoC and IP: Is the Role of Test Chips Changing at Advanced Foundry Nodes?

    TomWong
    TomWong

    Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs.

    Semiconductor designers have long been making test chips to validate…

    • 15 Jul 2019
  • Breakfast Bytes: Will American Scooters Follow Chinese Bikes?

    Paul McLellan
    Paul McLellan
    I spent the July 4 weekend in San Diego. My public service announcement is that if you go to San Diego, the first thing you should do is buy a week pass to all the museums in Balboa Park, and add on a discount admission to the zoo if you plan to...
    • 15 Jul 2019
  • Analog/Custom Design: Virtuoso Meets Maxwell: Learn Your Moves – We’re Doing an Edit-in-Concert

    Steve PDK Lee
    Steve PDK Lee
    This blog showcases the Edit-in-Concert technology available in the Cadence Virtuoso RF Solution, which lets designers view and edit die packages and their corresponding die layouts synchronously.
    • 14 Jul 2019
  • Verification: How to Verify Performance of Complex Interconnect-Based Designs?

    Thierry Berdah
    Thierry Berdah

    With more and more SoCs employing sophisticated interconnect IP to link multiple processor cores, caches, memories, and dozens of other IP functions, the designs are enabling a new generation of low-power servers and high-performance mobile devices. The complexity of the interconnects and their advanced configurability contributes to already formidable design and verification challenges which lead to the following questions…

    • 14 Jul 2019
  • Breakfast Bytes: Sunday Brunch Video for 14th July 2019

    Paul McLellan
    Paul McLellan
    https://youtu.be/HO3cViPU6Mw Made at Slovensky Raj, Slovakia (camera Gary Bengier) Monday: Carry: From Logarithms to Mechanical Calculators Tuesday: Carry: Babbage's Engines Wednesday: Carry: Electronics Thursday: NXP: Can Silicon Valley Rea...
    • 14 Jul 2019
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